ARM DDI 0301H
ID012310
2.12
Exceptions ............................................................................................................. 2-36
2.13
Software considerations ........................................................................................ 2-59
3.1
3.2
4.1
4.2
4.3
Endian support ......................................................................................................... 4-6
4.4
4.5
4.6
4.7
5.1
5.2
Branch prediction ..................................................................................................... 5-4
5.3
Return stack ............................................................................................................. 5-7
5.4
Memory Barriers ...................................................................................................... 5-8
5.5
6.1
About the MMU ........................................................................................................ 6-2
6.2
TLB organization ...................................................................................................... 6-4
6.3
Memory access sequence ....................................................................................... 6-7
6.4
6.5
Memory access control .......................................................................................... 6-11
6.6
6.7
6.8
MMU aborts ........................................................................................................... 6-27
6.9
MMU fault checking ............................................................................................... 6-29
6.10
6.11
6.12
MMU descriptors .................................................................................................... 6-43
6.13
7.1
7.2
Cache organization .................................................................................................. 7-3
7.3
Tightly-coupled memory .......................................................................................... 7-7
7.4
DMA ....................................................................................................................... 7-10
7.5
7.6
Write buffer ............................................................................................................ 7-16
8.1
8.2
8.3
8.4
8.5
8.6
8.7
Endianness ............................................................................................................ 8-38
8.8
Locked access ....................................................................................................... 8-39
9.1
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