Table 6-3 Cache Policy Bits; Table 6-4 Inner And Outer Cache Policy Implementation Options - ARM ARM1176JZF-S Technical Reference Manual

Cache policy
Inner Noncacheable
Inner Write-Through
Inner Write-Back
Outer Noncacheable
Outer Write-Through
Outer Write-Back
ARM DDI 0301H
ID012310
Table 6-3 shows how the MMU and cache interpret the cache policy bits.
You can choose the write allocation policy that an implementation supports. The Allocate On
Write and No Allocate On Write cache policies indicate the preferred allocation policy for a
memory region, but you must not rely on the memory system implementing that policy. The
processor does not support Inner Allocate on Write.
Not all Inner and Outer cache policies are mandatory. Table 6-4 lists possible implementation
options.
Implementation options
Mandatory.
Mandatory.
Optional. If not supported, the memory system must implement this as
Inner Write-Through.
Mandatory.
Optional. If not supported, the memory system must implement this as
Outer Non-cacheable.
Optional. If not supported, the memory system must implement this as
Outer Write-Through.
When the MMU is off and TexRemap=0:
• All data accesses are treated as Shared, Inner Strongly Ordered, Outer Non-cacheable.
• Instruction accesses are treated as Non-Shared, Inner and Outer Write-Through, No
Allocate on Write, when the Instruction Cache is on, I=1, bit [12], see c1, Control Register
on page 3-44.
Instruction accesses are treated as Shared, Inner Strongly Ordered, Outer Non-Cacheable,
when the Instruction Cache is off, see Behavior with MMU disabled on page 6-9.
TexRemap=1 configuration
Only three bits, TEX[0], C, and B, are relevant in this configuration. The OS can use the
TEX[2:1] bits to manage the page tables.
In this configuration the processor provides the OS with a remap capability for the memory
attribute. Two CP15 registers, the Primary Region Remap Register (PRRR) and the Normal
Memory Region Register (NMRR) come into effect.
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BB or AA bits Cache policy
b00 Noncacheable
b01 Write-Back cached, Write Allocate
b10 Write-Through cached, No Allocate on Write
b11 Write-Back cached, No Allocate on Write

Table 6-4 Inner and Outer cache policy implementation options

Memory Management Unit

Table 6-3 Cache policy bits

Supported by
the processor
Yes
Yes
Yes
System-dependent
System-dependent
System-dependent
6-16