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Bits
Name
[31]
EX
[30]
EN
[29]
-
[28]
FP2V
[27:11]
-
ARM DDI 0301H
ID012310
The INV flag, FPEXC[7], signals Input exceptions. An Input exception is a condition when the
hardware cannot process one or more input operands according to the architectural
specifications. This includes subnormal inputs when the VFP11 coprocessor is not in
flush-to-zero mode and NaNs when the VFP11 coprocessor is not in default NaN mode.
The UFC flag, FPEXC[3], is set whenever an operation has the potential to generate a result that
is lower than the minimum threshold for the destination precision.
The OFC flag, FPEXC[2], is set whenever an operation has the potential to generate a result that,
after rounding, exceeds the largest representable number in the destination format.
The IOC flag, FPEXC[0], is set whenever an operation has the potential to generate a result that
cannot be represented or is not defined.
Note
To prevent an infinite loop of exceptions, the support code must clear the EX flag, FPEXC[31],
immediately on entry to the exception code. All exception flags must be cleared before returning
from exception code to user code.
Figure 20-7 shows the FPEXC bit fields.
31 30 29 28
27
FP2V
SBZ
EN
EX
Table 20-8 lists the bit fields of the FPEXC register.
Description
Exception flag.
When EX is set, the VFP11 coprocessor is in the exceptional state.
EX must be cleared by the exception handling routine.
VFP enable bit.
Setting EN enables the VFP11 coprocessor. Reset clears EN.
Should Be Zero.
FPINST2 instruction valid flag.
Set when FPINST2 contains a valid instruction.
FP2V must be cleared by the exception handling routine.
Should Be Zero.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
SBZ
Figure 20-7 Floating-Point Exception Register
Table 20-8 Encoding of the Floating-Point Exception Register
VFP Programmer's Model
11
10
8 7 6
4 3 2 1 0
VECITR
SBZ
INV
UFC
OFC
SBZ
IOC
20-17
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