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18.1
About the VFP11 coprocessor
ARM DDI 0301H
ID012310
The VFP11 coprocessor is an implementation of the ARM Vector Floating-point Architecture
(VFPv2). It provides low-cost floating-point computation that is fully compliant with the IEEE
Standard for Binary Floating-Point Arithmetic, referred to in this document as the IEEE 754
standard. The VFP11 coprocessor supports all of the VFP addressing modes described for
vector operations in the ARM Architecture Reference Manual.
The VFP11 coprocessor is optimized for:
•
high data transfer bandwidth through 64-bit split load and store buses
•
fast hardware execution of a high percentage of operations on normalized data, resulting
in higher overall performance while providing full IEEE 754 standard support when
required
•
hardware divide and square root operations in parallel with other arithmetic operations to
reduce the impact of long-latency operations
•
near IEEE 754 standard compatibility in RunFast mode without support code assistance,
providing determinable run-time calculations for all input data
•
low power consumption, small die size, and reduced kernel code.
The VFP11 coprocessor is an ARM enhanced numeric coprocessor that provides operations that
are compatible with the IEEE 754 standard. Designed for the ARM11 family of cores, the
VFP11 coprocessor fully supports single-precision and double-precision add, subtract, multiply,
divide, multiply and accumulate, and square root operations. Conversions between
floating-point data formats and ARM integer word format are provided, with special operations
to perform the conversion in round-towards-zero mode for high-level language support.
The VFP11 coprocessor provides a performance-power-area solution for embedded
applications and high performance for general-purpose applications.
Note
This manual describes only VFP11-specific implementation issues. Refer also to the Vector
Floating-point Architecture section of the ARM Architecture Reference Manual.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Introduction to the VFP coprocessor
18-2
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