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Do Not Modify (DNM)
Double-precision value
Doubleword
Doubleword-aligned
EmbeddedICE logic
EmbeddedICE-RT
Embedded Trace Macrocell (ETM)
Enabled exception
Endianness
ETM
Event
Exception
Exceptional state
Exception service routine
ARM DDI 0301H
ID012310
In Do Not Modify fields, the value must not be altered by software. DNM fields read as
Unpredictable values, and must only be written with the same value read from the same field on
the same processor.
DNM fields are sometimes followed by RAZ or RAO in parentheses to show which way the bits
should read for future compatibility, but programmers must not rely on this behavior.
Consists of two 32-bit words that must appear consecutively in memory and must both be
word-aligned, and that is interpreted as a basic double-precision floating-point number
according to the IEEE 754-1985 standard.
A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.
A data item having a memory address that is divisible by eight.
An on-chip logic block that provides TAP-based debug support for ARM processor cores. It is
accessed through the TAP controller on the ARM core using the JTAG interface.
The JTAG-based hardware provided by debuggable ARM processors to aid debugging in
real-time.
A hardware macrocell that, when connected to a processor core, outputs instruction and data
trace information on a trace port. The ETM provides processor driven trace through a trace port
compliant to the ATB protocol.
An exception is enabled when its exception enable bit in the FPCSR is set. When an enabled
exception occurs, a trap to the user handler is taken. An operation that generates an exception
condition might bounce to the support code to produce the result defined by the IEEE 754
standard. The exception is then reported to the user trap handler.
Byte ordering. The scheme that determines the order in which successive bytes of a data word
are stored in memory. An aspect of the system's memory mapping.
See also Little-endian and Big-endian
See Embedded Trace Macrocell.
1 (Simple) An observable condition that can be used by an ETM to control aspects of a trace.
2 (Complex) A boolean combination of simple events that is used by an ETM to control aspects
of a trace.
A fault or error event that is considered serious enough to require that program execution is
interrupted. Examples include attempting to perform an invalid memory access, external
interrupts, and undefined instructions. When an exception occurs, normal program flow is
interrupted and execution is resumed at the corresponding exception vector. This contains the
first instruction of the interrupt handler to deal with the exception.
When a potentially exceptional instruction is issued, the VFP11 coprocessor sets the EX bit,
FPEXC[31], and loads a copy of the potentially exceptional instruction in the FPINST register.
If the instruction is a short vector operation, the register fields in FPINST are altered to point to
the potentially exceptional iteration. When in the exceptional state, the issue of a trigger
instruction to the VFP11 coprocessor causes a bounce.
See also Bounce, Potentially exceptional instruction, and Trigger instruction.
See Interrupt handler.
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