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13.3.10 CP14 c112-c113, Watchpoint Control Registers (WCR)
Binary address
Opcode_2
b111
Read/write
Bits
attributes
[31:21]
UNP/SBZP
[20]
RW
[19:16]
RW
ARM DDI 0301H
ID012310
For the second case a WRP and a BRP with context ID comparison capability have to be linked.
A debug event is generated when both the DMVA and the context ID pair match simultaneously.
Table 13-14 lists the bit field definitions for the Watchpoint Value Registers.
These registers contain the necessary control bits for setting:
•
watchpoints
•
linked watchpoints.
Table 13-15 lists the Watchpoint Control Registers that the processor implements.
Register
number
CRm
b0000-b0001
c112-c113
Figure 13-7 shows the format of the Watchpoint Control Registers.
31
31
UNP/SBZP
UNP/SBZP
Table 13-16 lists the bit field definitions for the Watchpoint Control Registers.
Reset
Description
value
-
Reserved.
-
Enable linking bit:
0 = Linking disabled
1 = Linking enabled.
When this bit is set, this watchpoint is linked with the context ID holding BRP
selected by the linked BRP field.
-
Linked BRP. The binary number encoded here indicates a context ID holding BRP
to link this WRP with.
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Table 13-14 Watchpoint Value Registers, bit field definitions
Bits
Read/write attributes
[31:2]
RW
[1:0]
UNP/SBZP
Table 13-15 Processor Watchpoint Control Registers
CP14 debug register name
Watchpoint Control Registers 0-1
21 20 19
21 20 19
16 15
16 15
E Linked BRP
E Linked BRP
Secure watchpoint match
Figure 13-7 Watchpoint Control Registers, format
Table 13-16 Watchpoint Control Registers, bit field definitions
Reset value
Description
-
Watchpoint address
-
-
Abbreviation
WCR0-1
14 13
9 8
9 8
Byte
Byte
UNP/SBZP
address
address
select
select
Debug
Context ID
capable?
-
5 4 3 2 1 0
5 4 3 2 1 0
L/S
L/S
S
S
W
W
13-21
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