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22.10 Inexact exception
22.10.1 Exception enabled
22.10.2 Exception disabled
ARM DDI 0301H
ID012310
The result of an arithmetic operation on two floating-point values can have more significant bits
than the destination register can contain. When this happens, the result is rounded to a value that
the destination register can hold and is said to be inexact.
The Inexact exception occurs whenever:
•
a result is not equal to the computed result before rounding
•
an untrapped Overflow exception occurs
•
an untrapped Underflow exception occurs, and there is loss of accuracy.
Note
The Inexact exception occurs frequently in normal floating-point calculations and does not
indicate a significant numerical error except in some specialized applications. Enabling the
Inexact exception by setting the IXE bit, FPSCR[12], can significantly reduce the performance
of the VFP11 coprocessor.
The VFP11 coprocessor handles the Inexact exception differently from the other floating-point
exceptions. It has no mechanism for reporting inexact results to the software, but can handle the
exception without software intervention as long as the IXE bit, FPSCR[12], is cleared, disabling
Inexact exceptions.
If the IXE bit, FPSCR[12], is set, all CDP instructions are bounced to the support code without
any attempt to perform the calculation. The support code is then responsible for performing the
calculation, determining if any exceptions have taken place, and handling them appropriately. If
the support code detects an Inexact exception, it calls the Inexact user trap handler.
Note
•
The inexact exception takes priority over all other exceptions.
•
The inexact exception is taken precisely, unlike other exceptions. This means that when a
CDP is bounced, because it is potentially imprecise, the instruction can be found at the
address pointed to by R14-4 and is not stored in the FPINST register. There is never a
pre-trigger instruction in the FPINST2 register.
If the IXE bit, FPSCR[12], is not set, the VFP11 coprocessor writes the result to the destination
register and sets the IXC flag, FPSCR[4].
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VFP Exception Handling
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