Table 3-61 Data Fault Status Register Bit Functions; Figure 3-36 Data Fault Status Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.17 c5, Data Fault Status Register
Bits
[31:13]
[12]
[11]
[10]
[9:8]
ARM DDI 0301H
ID012310
MRC p15, 0, <Rd>, c3, c0, 0
MCR p15, 0, <Rd>, c3, c0, 0
The purpose of the Data Fault Status Register is to hold the source of the last data fault.
Table 3-61 lists the purposes of the individual bits in the Data Fault Status Register.
The Data Fault Status Register is:
• in CP15 c5
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-36 shows the bit arrangement in the Data Fault Status Register.
31
Table 3-61 shows how the bit values correspond with the Data Fault Status Register functions.
Field
Function
name
- UNP/SBZ.
SD Indicates if an AXI Decode or Slave error caused an abort. This is only valid for external
aborts. For all other aborts this Should Be Zero. See Fault status and address on
page 6-34:
0 = AXI Decode error caused the abort, reset value
1 = AXI Slave error caused the abort.
RW Indicates whether a read or write access caused an abort:
0 = Read access caused the abort, reset value
1 = Write access caused the abort.
S Part of the Status field. See Bits [3:0] in this table. The reset value is 0.
- Always read as 0. Writes ignored.
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; Read Domain Access Control Register
; Write Domain Access Control Register
UNP/SBZ

Figure 3-36 Data Fault Status Register format

Table 3-61 Data Fault Status Register bit functions

System Control Coprocessor
13 12 11 10 9 8 7
S R
S 0 0 Domain
D W
4 3 0
Status
3-64