Etm Interface Signals; Table A-13 Etm Interface Signals - ARM ARM1176JZF-S Technical Reference Manual

A.8

ETM interface signals

Name
ETMDA[31:3]
ETMDACTL[17:0]
ETMDD[63:0]
ETMDDCTL[3:0]
ETMEXTOUT[1:0]
ETMIA[31:0]
ETMIACTL[17:0]
ETMIASECCTL[1:0]
ETMIARET[31:0]
ETMPADV[2:0]
ETMPWRUP
nETMWFIREADY
ETMCPADDRESS[14:0]
ETMCPSECCTL[1:0]
ETMCPCOMMIT
ETMCPENABLE
ETMCPRDATA[31:0]
ETMCPWDATA[31:0]
ETMCPWRITE
EVNTBUS[19:0]
WFIPENDING
ARM DDI 0301H
ID012310
Table A-13 lists the ETM interface signals.
Direction Description
Output ETM data address.
Output ETM data control, address phase.
Output ETM data.
Output ETM data control, data phase.
Input ETM external event to be monitored.
Output ETM instruction address.
Output ETM instruction control.
Output TrustZone trace information.
Output ETM return instruction address.
Output ETM pipeline advance.
Input When HIGH, indicates that the ETM is powered up. When LOW, logic
supporting the ETM must be clock gated to conserve power.
Input When LOW, indicates ETM can accept Wait For Interrupt.
Output Coprocessor address.
Output Coprocessor Non-secure access and prohibited trace.
Output Coprocessor commit.
Output Coprocessor interface enable.
Input Coprocessor read data.
Output Coprocessor write data.
Output Coprocessor write control.
Output System metrics event bus.
Output Indicates a Pending Wait For Interrupt. Handshakes with
nETMWFIREADY.
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Signal Descriptions

Table A-13 ETM interface signals

A-15