Tlb Organization; Figure - ARM ARM1176JZF-S Technical Reference Manual

6.2

TLB organization

6.2.1 MicroTLB
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The following sections describe the TLB organization:
• MicroTLB
• Main TLB on page 6-5
• TLB control operations on page 6-5
• Page-based attributes on page 6-5
• Supersections on page 6-6.
The first level of caching for the page table information is a small MicroTLB of ten entries that
is implemented on each of the instruction and data sides. These entities are implemented in
logic, providing a fully associative lookup of the virtual addresses in a cycle. This means that a
MicroTLB miss signal is returned at the end of the DC1 cycle. In addition to the virtual address,
an Address Space IDentifier (ASID) and a NSTID are used to distinguish different address
mappings that might be in use.
The current ASID is a small identifier, eight bits in size, that is programmed using CP15 when
different address mappings are required. A memory mapping for a page or section can be
marked as being global or referring to a specific ASID. The MicroTLB uses the current ASID
in the comparisons of the lookup for all pages for which the global bit is not set.
The NSTID consists of one bit, and is automatically set when a new entry is written. The entry
is marked as Secure when the MicroTLB request is Secure, that is when it is performed when
the core is in Secure Monitor mode, whatever the value of the NS bit in the CP15 SCR register,
or in any Secure mode, NS bit in CP15 SCR = 0.
The MicroTLB returns the physical address to the cache for the address comparison, and also
checks the protection attributes in sufficient time to signal a Data Abort in the DC2 cycle. An
additional set of attributes, to be used by the cache line miss handler, are provided by the
MicroTLB. The timing requirements for these are less critical than for the physical address and
the abort checking.
You can configure MicroTLB replacement to be round-robin or random. By default the
round-robin replacement algorithm is used. The random replacement algorithm is designed to
be selected for rare pathological code that causes extreme use of the MicroTLB. With such code,
you can often improve the situation by using a random replacement algorithm for the
MicroTLB. You can only select random replacement of the MicroTLB if random cache
selection is in force, as set by the Control Register RR bit. If the RR bit is 0, then you can select
random replacement of the MicroTLB by setting the Auxiliary Control Register bit 3. This
register is only accessible in Secure Privileged modes.
Note
The RR bit is common to the Secure and Non-secure worlds.
All main TLB maintenance operations affect both the instruction and data MicroTLBs, causing
them to be flushed.
The virtual addresses held in the MicroTLB include the FCSE translation from Virtual Address
(VA) to Modified Virtual Address (MVA). For more information see the ARM Architecture
Reference Manual. The process of loading the MicroTLB from the main TLB includes the
FCSE translation if appropriate.
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Memory Management Unit
6-4