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8.5.6
Noncacheable LDM3
8.5.7
Noncacheable LDM4
ARM DDI 0301H
ID012310
The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for
Noncacheable LDM3s addressing words 0 to 5 are shown in:
•
Table 8-18 for a load from Strongly Ordered or Device memory
•
Table 8-19 for a load from Noncacheable memory or when the cache is disabled.
A Noncacheable LDM3 addressing word 6 or 7 is split into two operations as shown in
Table 8-20.
Table 8-18 Noncacheable LDM3, Strongly Ordered or Device memory
Address[4:0]
0x00
, word 0
0x04
, word 1
0x08
, word 2
0x0C
, word 3
, word 4
0x10
, word 5
0x14
Table 8-19 Noncacheable LDM3, Noncacheable memory or cache disabled
Address[4:0]
, word 0
0x00
0x04
, word 1
0x08
, word 2
0x0C
, word 3
0x10
, word 4
, word 5
0x14
The values of ARADDRRW, ARBURSTRW, ARSIZERW, and ARLENRW for
Noncacheable LDM4s addressing words 0 to 4 are shown in:
•
Table 8-21 on page 8-19 for a load from Strongly Ordered or Device memory
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Table 8-17 Noncacheable LDRD or LDM2 from word 7
Address[4:0]
, word 7
0x1C
ARADDRRW
ARBURSTRW
0x00
Incr
0x04
Incr
0x08
Incr
0x0C
Incr
Incr
0x10
Incr
0x14
ARADDRRW
ARBURSTRW
Incr
0x00
0x04
Incr
0x08
Incr
0x0C
Incr
0x10
Incr
Incr
0x14
Table 8-20 Noncacheable LDM3 from word 6, or 7
Address[4:0]
, word 6
0x18
, word 7
0x1C
Level Two Interface
Operations
LDR from
+ LDR from
0x1C
ARSIZERW
ARLENRW
32-bit
3 data transfers
32-bit
3 data transfers
32-bit
3 data transfers
32-bit
3 data transfers
32-bit
3 data transfers
32-bit
3 data transfers
ARSIZERW
ARLENRW
64-bit
2 data transfers
64-bit
2 data transfers
64-bit
2 data transfers
64-bit
2 data transfers
64-bit
2 data transfers
64-bit
2 data transfers
Operations
LDM2 from
+ LDR from
0x18
LDR from
+ LDM2 from
0x1C
0x00
0x00
0x00
8-18
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