Figure 3-5 Cache Master Valid Registers; Figure 3-6 Dma Control And Configuration Registers - ARM ARM1176JZF-S Technical Reference Manual

3.1.7 DMA control
ARM DDI 0301H
ID012310
CRn Opcode_1
c15
Read-only
To use the Cache Master Valid Registers you read or write the individual registers that make up
the group, see Use of the system control coprocessor on page 3-12.
The Cache Master Valid Registers behave as a set of bits that define the cache contents as valid
or invalid. The number of bits is a function of the cache size.
The purpose of the DMA control registers is to:
• enable software to control DMA
• transfer large blocks of data between the TCM and an external memory
• determine accessibility
• select DMA channel.
The Enable, Control, Internal Start Address, External Start Address, Internal End Address,
Channel Status, and Context ID Registers are multiple registers with one register of each for
each channel that is implemented.
The DMA control registers consist of five 32-bit read-only registers, three 32-bit write-only
registers and seven 32-bit read/write registers. Figure 3-6 shows the arrangement of registers.
CRn Opcode_1
c11
One register per channel selected
by DMA Channel Number Register
Read-only
To use the DMA control and configuration registers you read or write the individual registers
that make up the group, see Use of the system control coprocessor on page 3-12.
Code can execute several DMA operations while in User mode if these operations are enabled
by the DMA User Accessibility Register.
If DMA control registers attempt to execute a privileged operation in User mode the processor
takes an Undefined instruction trap.
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CRm Opcode_2
3 c8
c12
Read/write

Figure 3-5 Cache Master Valid Registers

CRm Opcode_2
c0
1
2
3
c1
c2
c3
1
2
c4
c5
c6
c7
c8
c15
0
Read/write Write-only

Figure 3-6 DMA control and configuration registers

System Control Coprocessor
Instruction Cache Master Valid Register
Data Cache Master Valid Register
Write-only Accessible in User mode
Present
Queued DMA Identification
and Status Registers
Running
Interrupting
DMA User Accessibility Register
DMA Channel Number Register
Stop
DMA Enable
Start
Registers
Clear
DMA Control Register
DMA Internal Start Address Register
DMA External Start Address Register
DMA Internal End Address Register
DMA Channel Status Register
DMA Context ID Register
Accessible in User mode
3-9