Figure 11-3 Coprocessor Pipeline - ARM ARM1176JZF-S Technical Reference Manual

11.2.4 Pipeline control
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The core can cancel an instruction currently in the coprocessor Ex1 stage by sending a signal
with the token passed down the cancel queue. When a coprocessor instruction reads the Ex6
stage it might retire. How it retires depends on the instruction:
• Load instructions retire when they find load data available in the load data queue, see
Loads on page 11-16
• Store instructions retire as soon as they leave the Ex1 stage, and are removed from the
pipeline, see Stores on page 11-17
• CDP instructions retire when they read a token passed by the core down the finish queue.
Figure 11-2 on page 11-5 shows how data transfer uses the load data and store data queues, and
Data transfer on page 11-15 explains this.
The coprocessor pipeline is very similar to the core pipeline, but lacks the fetch stages.
Instructions are passed from the core directly into the Decode stage of the coprocessor pipeline,
that takes the form of a FIFO queue.
The Decode stage then decodes the instruction, rejecting non-coprocessor instructions and any
coprocessor instructions containing a nonmatching coprocessor number.
The length of any vectored data transfer is also decided at this point and sent back to the core.
The decoded instruction then passes into the issue (I) stage. This stage decides if this particular
instance of the instruction can be accepted. If it cannot, because it addresses a non-existent
register, the instruction is bounced, informing the core that it cannot be accepted.
If the instruction is both valid and executable, it then passes down the execution pipeline, Ex1
to Ex6. At the bottom of the pipeline, in Ex6, the instruction waits for retirement. It can do this
when it receives a matching token from another queue fed by the core.
Figure 11-3 shows the coprocessor pipeline, the main fields within each stage, and the main
control signals. Each stage controls the flow of information from the previous stage in the
pipeline by passing its Enable signal back. When a pipeline stage is not enabled, it cannot accept
information from the previous stage.
I stage
Ex1 stage
Ex2 stage
Ex3 to Ex5 stages
(not shown)
Ex6 stage
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From core pipeline
Instruction queue and decoder
Decoded instruction Tag Full
Decoded instruction Tag Full
Decoded instruction Tag Full
Stages Ex3 to Ex5 are same as stage Ex2
Decoded instruction Tag Full

Figure 11-3 Coprocessor pipeline

Coprocessor Interface
Stall D
Enable
Flags
I stage control Stall I
Enable
Flags
Ex1 stage control Stall Ex1
Enable
Flags
Ex2 stage control
Enable
Flags
Ex6 stage control Stall Ex6
11-6