Table 3-66 Results Of Access To The Instruction Fault Address Register - ARM ARM1176JZF-S Technical Reference Manual

3.2.20 c6, Watchpoint Fault Address Register
3.2.21 c6, Instruction Fault Address Register
3.2.22 c7, Cache operations
ARM DDI 0301H
ID012310
Access to the Watchpoint Fault Address register through the system control coprocessor is
deprecated, see CP14 c6, Watchpoint Fault Address Register (WFAR) on page 13-12.
The purpose of the Instruction Fault Address Register (IFAR) is to hold the address of
instructions that cause a prefetch abort.
The IFAR is:
• in CP15 c6
• a 32-bit read/write register banked for Secure and Non-secure worlds
• accessible in privileged modes only.
The Instruction Fault Address Register bits [31:0] contain the Instruction Fault MVA. The reset
value is 0.
Table 3-66 lists the results of attempted access for each mode.

Table 3-66 Results of access to the Instruction Fault Address Register

Secure Privileged
Read Write
Secure data Secure data
To use the IFAR read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c6
• CRm set to c0
• Opcode_2 set to 2.
For example:
MRC p15, 0, <Rd>, c6, c0, 2
MCR p15, 0, <Rd>, c6, c0, 2
A write to this register sets the IFAR to the value of the data written. This is useful for a debugger
to restore the value of the IFAR.
The purpose of c7 is to:
• control these operations:
— clean and invalidate instruction and data caches, including range operations
— prefetch instruction cache line
— Flush Prefetch Buffer
— flush branch target address cache
— virtual to physical address translation.
• implement the Data Synchronization Barrier (DSB) operation
• implement the Data Memory Barrier (DMB) operation
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read Write
Non-secure data Non-secure data
; Read Instruction Fault Address Register
; Write Instruction Fault Address Register
System Control Coprocessor
User
Undefined exception
3-69