Table 3-153 Results Of Access To The Tlb Lockdown Access Registers - ARM ARM1176JZF-S Technical Reference Manual

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Bits
Field name
[25]
SPV
[24:11]
SBZ
[10:7]
Domain
[6]
XN
[5:3]
TEX
[2]
C
[1]
B
[0]
S
ARM DDI 0301H
ID012310
Table 3-152 TLB Lockdown Attributes Register bit functions (continued)
Function
Indicates that this page table entry supports sub-pages. Page table entries that support
sub-pages must be marked as Global, see c15, TLB lockdown access registers on page 3-149:
0 = Sub-pages are not valid
1 = Sub-pages are valid.
UNP/SBZ.
Specifies the Domain number for the page table entry.
Specifies Execute Never attribute: when set, the contents of the memory region that this page
table entry describes cannot be executed as code. An attempt to execute an instruction in this
region results in a permission fault:
0 = Can execute
1 = Cannot execute.
TEX[2:0] bits. Describes the memory region attributes. See Memory region attributes on
page 6-14.
C bit. Describes the memory region attributes. See Memory region attributes on page 6-14.
B bit. Describes the memory region attributes. See Memory region attributes on page 6-14.
Indicates if the memory region that this page table entry describes is shareable:
0 = Region is not shared
1 = Region is shared.
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH
result in an Undefined exception, see TrustZone write access disable on page 2-9.
Table 3-153 lists the results of attempted access for each mode.

Table 3-153 Results of access to the TLB lockdown access registers

Secure Privileged
Read
Write
Data
Data
To read or write a TLB Lockdown entry, you must use this procedure:
1.
Write TLB Lockdown Index Register to select the required TLB Lockdown entry.
2.
Read or write TLB Lockdown VA Register.
3.
Read or write TLB Lockdown Attributes Register.
4.
Read or write TLB Lockdown PA Register. For writes, this sets the valid bit, enabling the
complete new entry to be used.
This procedure must not be interruptible, so your code must disable interrupts before it accesses
the TLB lockdown access registers.
Note
Software must avoid the creation of inconsistencies between the main TLB entries and the
entries already loaded in the micro-TLBs.
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read
Write
Undefined exception
Undefined exception
System Control Coprocessor
User
Undefined exception
3-152

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