ARM ARM1176JZF-S Technical Reference Manual page 276

ARM DDI 0301H
ID012310
You use the System Validation Operations Register to start and stop the reset, interrupt, fast
interrupt, and external debug request counters. When the system starts any of these counters,
they count up incrementing by one every core clock cycle, until they wrap around. When the
counters wrap around they cause nVALRESET, nVALIRQ, nVALFIQ, or VALEDBGRQ to
go LOW depending on the operation. You can use these outputs to generate system Reset,
Interrupt request, Fast Interrupt request, or External Debug Request events. You can use the
System Validation Counter Register to set the start value of the counters, see c15, System
Validation Counter Register on page 3-140. Any number of events can occur simultaneously.
When you use the Validation Trickbox Operations Register to start a counter, there is one clock
cycle delay, that generally corresponds to one instruction, before the count begins. If you require
an event to occur on the next instruction, insert a NOP instruction between the MCR instruction,
to the System Validation Operations Register, that starts the counter and the instruction on which
you want the event to occur.
You must leave two clock cycles, that generally corresponds to two instructions, between a write
to a counter with the System Validation Counter Register and the start of that count with the
System Validation Operations Register.
After the system stops the reset, interrupt or fast interrupt counters, or after handling the events
they cause, you must explicitly clear the counters to return them to their System performance
monitoring function. To do this set bits in <Rn> and write to the Performance Monitor Control
Register to clear the relevant overflow flags:
• bit [10] to clear the reset counter
• bit [9] to clear the fast interrupt counter
• bit [8] to clear the interrupt counter.
You must carry out this operation with a read-modify-write sequence to avoid changes to other
bits, see c15, Performance Monitor Control Register on page 3-133. You do not have to clear
the external debug request counter explicitly in this way because it is not used for system
performance monitoring.
The reset, interrupt, and fast interrupt counters reuse the Cycle Count Register, Count Register
0 and Count Register 1 of the System performance monitor registers respectively, see System
performance monitor on page 3-10. As a result you must not perform read or write operations
to the System Validation Counter Register when the System performance monitor registers are
in use.
The System Validation Operations Register is write only and attempts to read this register are
reserved and return 0x00000000
To schedule system validation events follow this procedure:
1. Modify the Secure User and Non-secure Access Validation Control Register to permit
access from User or Non-secure modes if this is required.
2. Use the Validation Trickbox Counter Register to load the required counter with
minus the number of core clock cycles to wait before the event occurs.
3. Use the Validation Trickbox Operations Register to start the required counter.
4. Use the appropriate Validation Trickbox Operations Register to stop the required counter,
after the event has occurred or as necessary.
5. Use the Performance Monitor Control Register to reset the counters and return them to
System performance monitoring functionality.
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System Control Coprocessor
0xFFFFFFFF
3-144