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11.4.4
Cancel queue
11.4.5
Finish queue
ARM DDI 0301H
ID012310
The core might want to cancel an instruction that it has already passed on to the coprocessor.
This can happen if the instruction fails its condition codes, that requires the instruction to be
removed from the instruction stream in both the core and the coprocessor.
The queue, a standard queue, as Token queue management on page 11-9 describes, is maintained
by the coprocessor and is read by the coprocessor Ex1 stage.
The cancel queue provides an interface to the core through the following signals, that are all
driven by the core:
ACPCANCELV
This signal is asserted when valid data are available from the core. It must be
clocked directly into the buffer A flag, unless the queue is full, when it is ignored.
ACPCANCEL
This is the cancel command being passed to the coprocessor from the core, and
must be clocked into buffer A.
ACPCANCELT[3:0]
This is the flush tag associated with the cancel command, and must be clocked
into the tag associated with buffer A.
The coprocessor Ex1 stage reads the cancel queue, that then acts on the value of the queued
ACPCANCEL signal by removing the instruction from the Ex1 stage if the signal is set, and
not passing it on to the Ex2 stage.
The finish queue maintains synchronism at the end of the pipeline by providing permission for
CDP instructions in the coprocessor pipeline to retire. The queue, a standard queue, as Token
queue management on page 11-9 describes, is maintained by the coprocessor and is read by the
coprocessor Ex6 stage.
The finish queue provides an interface to the core using the ACPFINISHV signal, that the core
drives.
This signal is asserted to indicate that the instruction in the coprocessor Ex6 stage can retire. It
must be clocked directly into the buffer A flag, unless the queue is full, when it is ignored.
The finish queue is read by the coprocessor Ex6 stage. It can retire a CDP instruction if the finish
queue is not empty.
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Coprocessor Interface
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