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A.2
Static configuration signals
Name
BIGENDINIT
CFGBIGEND
INITRAM
UBITINIT
VINITHI
ARM DDI 0301H
ID012310
Table A-2 lists the processor static configuration signals.
Direction
Description
Input
When HIGH indicates v5 Big-endian mode.
Output
Current state of CP15 Bigend bit.
Input
Determines the reset value of the En bit, bit 0, of the Instruction TCM Region Register.
When HIGH this bit resets to 1 and the Instruction TCM is enabled on reset. For more
information see c9, Instruction TCM Region Register on page 3-91.
Input
When HIGH indicates ARMv6 unaligned behavior.
Input
When HIGH indicates High Vecs mode.
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Signal Descriptions
Table A-2 Static configuration signals
A-4
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