Overflow Exception; Table 22-6 Rounding Mode Overflow Results - ARM ARM1176JZF-S Technical Reference Manual

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22.8

Overflow exception

22.8.1
Exception enabled
22.8.2
Exception disabled
ARM DDI 0301H
ID012310
When the OFE bit, FPSCR[10], is set, the hardware detects overflow pessimistically based on
the preliminary calculation of the final exponent value. If the OFE bit is not set, the hardware
detects overflow conclusively.
Setting the OFE bit enables overflow exceptions. The VFP11 coprocessor detects most overflow
conditions conclusively, but it detects some based on the possibility of overflow. The initial
computation of the result exponent might be the maximum exponent or one less than the
maximum exponent of the destination precision. Then the possibility of overflow because of
significand overflow or rounding exists, but cannot be known in the first Execute stage. The
VFP11 coprocessor bounces on such cases and uses the support code to determine the
exceptional status of the operation.
If there is no overflow, the support code writes the computed result to the destination register
and does not set the OFC flag, FPSCR[2]. If there is an overflow, the intermediate result is
written to the destination register, OFC is set, and the Overflow user trap handler is called. The
support code sets or clears the IXC flag, FPSCR[4], as appropriate.
When the VFP11 coprocessor detects a potential overflow condition, the EX flag, FPEXC[31],
and the OFC flag, FPEXC[2], are set. The OFC flag in the FPSCR register, FPSCR[2], is not set
by the hardware and must be set by the support code before calling the user trap handler. The
source and destination registers for the instruction are unchanged in the VFP11 register file. See
Arithmetic exceptions on page 22-20 for the conditions that cause an overflow bounce.
Clearing the OFE bit disables overflow exceptions. A correctly signed infinity or the largest
signed finite number for the destination precision is written to the destination register as
Table 22-6 lists. The OFC and IXC flags, FPSCR[2] and FPSCR[4], are set.
Rounding mode
Round to nearest
Round towards zero
Round towards plus infinity
Round towards minus infinity
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Table 22-6 Rounding mode overflow results

Result
Infinity, with the sign of the intermediate result.
Largest magnitude value for the destination size, with the
sign of the intermediate result.
Positive infinity if positive overflow. Largest negative value
for the destination size if negative overflow.
Largest positive value for the destination size if positive
overflow. Negative infinity if negative overflow.
VFP Exception Handling
22-16

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