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Chapter 7
Level One Memory System
This chapter describes the processor level one memory system. It contains the following sections:
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ARM DDI 0301H
ID012310
About the level one memory system on page 7-2
Cache organization on page 7-3
Tightly-coupled memory on page 7-7
DMA on page 7-10
TCM and cache interactions on page 7-12
Write buffer on page 7-16.
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