D4.4 Pmcr, Performance Monitors Control Register - ARM Cortex-A76 Core Technical Reference Manual

D4.4 PMCR, Performance Monitors Control Register
The PMCR provides details of the Performance Monitors implementation, including the number of
counters implemented, and configures and controls the counters.
Bit field descriptions
PMCR is a 32-bit register, and is part of the Performance Monitors registers functional group.
IMP, [31:24]
IDCODE, [23:16]
N, [15:11]
RES0, [10:7]
LC, [6]
DP, [5]
X, [4]
100798_0300_00_en
31 24 23
IMP
0
RES
Indicates the implementer code. The value is:
ASCII character 'A' - implementer is Arm Limited.
0x41
Identification code. The value is:
Cortex-A76 core.
0x0B
Identifies the number of event counters implemented.
The core implements six event counters.
0b00110
Reserved.
RES0
Long cycle count enable. Determines which PMCCNTR bit generates an overflow recorded in
PMOVSR[31]. The overflow event is generated on a 32-bit or 64-bit boundary. The possible
values are:
Overflow event is generated on a 32-bit boundary, when an increment changes
0b0
PMCCNTR[31] from 1 to 0. This is the reset value.
Overflow event is generated on a 64-bit boundary, when an increment changes
0b1
PMCCNTR[63] from 1 to 0.
Arm deprecates use of PMCR.LC =
Disable cycle counter CCNT when event counting is prohibited. The possible values are:
Cycle counter operates regardless of the non-invasive debug authentication
0b0
settings. This is the reset value.
Cycle counter is disabled if non-invasive debug is not permitted and enabled.
0b1
Copyright © 2016–2018 Arm Limited or its affiliates. All rights

D4.4 PMCR, Performance Monitors Control Register

16 15
IDCODE N
.
0b0
reserved.
Non-Confidential
D4 AArch32 PMU registers
11 10 7 6 5 4 3
X D
DP
LC
Figure D4-3 PMCR bit assignments
2 1 0
C P E
D4-441