Table 3-119 Dma Context Id Register Bit Functions; Table 3-120 Results Of Access To The Dma Context Id Register; Figure 3-64 Dma Context Id Register Format - ARM ARM1176JZF-S Technical Reference Manual

3.2.42 c11, DMA Context ID Register
DMA bit
0
1
ARM DDI 0301H
ID012310
The DMA Context ID Register for each channel contains the processor 32-bit Context ID of the
process that uses that channel.
The DMA Context ID Register is:
• in CP15 c11
• a 32-bit read/write register for each DMA channel common to Secure and Non-secure
worlds
• accessible in privileged modes only.
Figure 3-64 shows the arrangement of bits in the DMA Context ID Register.
31
Table 3-119 lists how the bit values correspond with the DMA Context ID Register functions.
Bits Field name
[31:8] PROCID
[8:0] ASID
Access in the Non-secure world depends on the DMA bit, see c1, Non-Secure Access Control
Register on page 3-55. Table 3-120 lists the results of attempted access for each mode.
Secure Privileged
Read Write
Data Data
Data Data
To access the DMA Context ID register in a privileged mode set the DMA Channel Number
Register to the appropriate DMA channel and read or write CP15 with:
• Opcode_1 set to 0
• CRn set to c11
• CRm set to c15
• Opcode_2 set to 0.
MRC p15, 0, <Rd>, c11, c15, 0
MCR p15, 0, <Rd>, c11, c15, 0
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PROCID

Figure 3-64 DMA Context ID Register format

Table 3-119 DMA Context ID Register bit functions

Function
Extends the ASID to form the process ID and identify the current process
Holds the process ID value
Holds the ASID of the current process and identifies the current ASID
Holds the ASID value

Table 3-120 Results of access to the DMA Context ID Register

Non-secure Privileged
Read Write
Undefined exception Undefined exception
Data Data
; Read DMA Context ID Register
; Write DMA Context ID Register
System Control Coprocessor
8 7 0
ASID
User
Undefined exception
Undefined exception
3-120