Table 22-10 Fdiv Bounce Thresholds - ARM ARM1176JZF-S Technical Reference Manual

22.12.5 FDIV
22.12.6 FSQRT
ARM DDI 0301H
ID012310
The thresholds for divide are simple and based only on the difference of the exponents of the
dividend and the divisor. It is not possible in a divide operation for the significand to overflow
and cause an increment of the exponent. However, it is possible for the significand to require a
single bit left shift and the exponent to be decremented for normalization. To reduce logic
complexity, the overflow ranges are the same as those of the LSA operations in FADD and
FSUB on page 22-20. The underflow ranges include the minimum normal exponent,
single-precision and
0x001
The exponent values shown in Table 22-10 are in biased format.
Initial quotient exponent value
DP a SP b
> 0x7FF -
0x7FF -
0x7FE -
-
0x7FD
-
0x7FC
> >
0x47F 0xFF
0x47F 0xFF
0x47E 0xFE
0x47D 0xFD
0x47C 0xFC
0x3FF 0x7F
0x382 0x02
0x381 0x01
0x380 0x00
< 0x380 < 0x00
0x002 -
-
0x001
-
0x000
< -
0x000
a. DP = double-precision.
b. SP = single-precision.
It is not possible for FSQRT to overflow or underflow.
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for double-precision. Table 22-10 lists the FDIV bounce thresholds.
Float value
DP overflow
DP NaN or infinity
DP maximum normal
DP normal
DP normal
SP overflow
SP NaN or infinity
SP maximum normal
SP normal
SP normal
e = 0 bias value
SP normal
SP normal
SP subnormal
SP underflow
DP normal
DP normal
DP subnormal
DP underflow
VFP Exception Handling

Table 22-10 FDIV bounce thresholds

Condition in full-compliance mode
SP DP
- Bounce
- Bounce
- Bounce
- Bounce
- Normal
Bounce Normal
Bounce Normal
Bounce Normal
Bounce Normal
Normal Normal
Normal Normal
Normal Normal
Bounce Normal
Bounce Normal
Bounce Normal
- Normal
- Bounce
- Bounce
- Bounce
0x01 for
22-23