Figure 4-7 Load Signed Halfword, Big-Endian; Figure 4-8 Store Halfword, Little-Endian - ARM ARM1176JZF-S Technical Reference Manual

4.3.8 Store halfword, little-endian
4.3.9 Store halfword, big-endian
ARM DDI 0301H
ID012310
In Figure 4-7, SE0 means bit 15, B0 bit [7], sign extended.
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
The low 16 bits of the general-purpose register are stored into the memory with bits [7:0] written
to the addressed byte in memory, bits [15:8] to the incremental byte address in memory, as
Figure 4-8 shows.
If strict alignment fault checking is enabled and Address bit 0 is not zero, then a Data Abort is
generated and the MMU returns a Misaligned fault in the Fault Status Register.
The low 16 bits of the general-purpose register are stored into the memory with bits [15:8]
written to the addressed byte in memory, bits [7:0] to the incremental byte address in memory,
as Figure 4-9 on page 4-10 shows.
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Unaligned and Mixed-endian Data Access Support
Memory
7 0
Address
A[31:0]
B0 msbyte
+1 B1 lsbyte

Figure 4-7 Load signed halfword, big-endian

Register
31 23 15 7
x x b1 b0
Register
31 23 15
SE0 SE0
Memory
7
Address
A[31:0]
0
+1

Figure 4-8 Store halfword, little-endian

7 0
B0 B1
0
b0 lsbyte
b1 msbyte
4-9