Global Signals; Table A-1 Global Signals - ARM ARM1176JZF-S Technical Reference Manual

A.1

Global signals

Name
CLKIN
FREECLKIN
nPORESETIN
nRESETIN
nVFPRESETIN
STANDBYWFI
VFPCLAMP
RAMCLAMP
CPUCLAMP
ACLKENP
ACLKEND
ACLKENI
ACLKENRW
ARESETIn
ARESETRWn
ARESETPn
ARESETDn
ACLKI
ACLKRW
ACLKP
ACLKD
SYNCMODEREQI
SYNCMODEREQRW
SYNCMODEREQP
SYNCMODEREQD
SYNCMODEACKI
ARM DDI 0301H
ID012310
Table A-1 lists the processor global signals.
Free clocks are the free running clocks with minimal insertion delay for clocking the clock
gating circuitry. Free clocks must be balanced with the incoming clock signal, but not with the
clocks clocking the core logic.
Direction Description
Input Core clock
Input Free running version of the core clock
Input Power on reset, resets debug logic
Input Core reset, not for VFP
Input VFP reset
Output Indicates that the processor is in Standby mode
Input Controls clamping logic between core and VFP
Input Enables the clamp cells in Dormant mode
Input Enables the clamp cells between VDD Core and VDD SoC
Input Clock enable for the peripheral port to enable it to be clocked at a reduced rate
Input Clock enable for the DMA port to enable it to be clocked at a reduced rate
Input Clock enable for the instruction port to enable it to be clocked at a reduced rate
Input Clock enable for the data port to enable it to be clocked at a reduced rate
Input AXI reset for Instruction IEM Register Slice
Input AXI reset for Data IEM Register Slice
Input AXI reset for Peripheral IEM Register Slice
Input AXI reset for DMA IEM Register Slice
Input AXI clock for Instruction IEM Register Slice
Input AXI clock for Data IEM Register Slice
Input AXI clock for Peripheral IEM Register Slice
Input AXI clock for DMA IEM Register Slice
Input Request for synchronous or asynchronous mode of Instruction IEM Register
Slice
Input Request for synchronous or asynchronous mode of Data IEM Register Slice
Input Request for synchronous or asynchronous mode of Peripheral IEM Register
Slice
Input Request for synchronous or asynchronous mode of DMA IEM Register Slice
Output Acknowledge for synchronous or asynchronous mode of Instruction IEM
Register Slice
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Signal Descriptions

Table A-1 Global signals

A-2