Table 3-30 Instruction Set Attributes Register 1 Bit Functions; Figure 3-22 Instruction Set Attributes Register 1 Format; Table 3-31 Results Of Access To The Instruction Set Attributes Register 1 - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
31 28 27 24 23
- -
Table 3-30 lists how the bit values correspond with the Instruction Set Attributes Register 1
functions.
Bits Field name
[31:28] -
[27:24] -
[23:20] -
[19:16] -
[15:12] -
[11:8] -
[7:4] -
[3:0] -
Table 3-31 lists the results of attempted access for each mode.

Table 3-31 Results of access to the Instruction Set Attributes Register 1

Secure Privileged
Read Write
Data Undefined exception
To use the Instruction Set Attributes Register 1 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c2
• Opcode_2 set to 1.
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Non-Confidential, Unrestricted Access
20 19 16 15
- -

Figure 3-22 Instruction Set Attributes Register 1 format

Table 3-30 Instruction Set Attributes Register 1 bit functions

Function
Indicates support for Java instructions.
0x1 , ARM1176JZF-S processors support BXJ and J bit in PSRs.
Indicates support for interworking instructions.
, ARM1176JZF-S processors support:
0x2
• BX, and T bit in PSRs
• BLX, and PC loads have BX behavior.
Indicates support for immediate instructions.
0x0 , no support in ARM1176JZF-S processors.
Indicates support for if then instructions.
, no support in ARM1176JZF-S processors.
0x0
Indicates support for sign or zero extend instructions.
0x2 , ARM1176JZF-S processors support:
• SXTB, SXTB16, SXTH, UXTB, UXTB16, and UXTH
• SXTAB, SXTAB16, SXTAH, UXTAB, UXTAB16, and UXTAH.
Indicates support for exception 2 instructions.
, ARM1176JZF-S processors support SRS, RFE, and CPS.
0x1
Indicates support for exception 1 instructions.
0x1 , ARM1176JZF-S processors support LDM(2), LDM(3) and STM(2).
Indicates support for endianness control instructions.
, ARM1176JZF-S processors support SETEND and E bit in PSRs.
0x1
Non-secure Privileged
Read Write
Data Undefined exception
System Control Coprocessor
12 11 8 7
- - -
User
Undefined exception
4 3 0
-
3-38