Branches; Table 16-11 Branch Instruction Cycle Timing Behavior - ARM ARM1176JZF-S Technical Reference Manual

16.8

Branches

ARM DDI 0301H
ID012310
This section describes the cycle timing behavior for the B, BL, and BLX instructions.
Branches are subject to dynamic, static and return stack predictions. Table 16-11 lists example
branch instructions and their cycle timing behavior.
Example instruction
B <immed>
B<immed>, BL<immed>, BLX<immed>
B<immed>, BL<immed>, BLX<immed>
B<immed>, BL<immed>, BLX<immed>
B<immed>, BL<immed>, BLX<immed>
BX R14
BX R14
BX R14
BX <cond> R14
BX <cond> <reg>
BX <cond> <reg>
a. Mispredicted branches, including taken unpredicted branches, takes a varying
number of cycles to execute depending on their distance from a flag setting
instruction. The timing behavior is:
Cycle = MAX (MaxCycles - FlagCycleDistance, MinCycles).
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Table 16-11 Branch instruction cycle timing behavior

Cycle
s
0
1
1
4
a
5-7
4
7
5
a
5-7
, 1
BLX <cond> <reg>
, BLX <cond> <reg> a
5-7
Cycle Timings and Interlock Behavior
Comment
Folded dynamic prediction
Not-folded dynamic prediction
Correct not-taken static prediction
Correct taken static prediction
Incorrect dynamic/static prediction
Correct return stack prediction
Incorrect return stack prediction
Empty return stack
Conditional return
If not taken
If taken
16-14