ARM ARM1176JZF-S Technical Reference Manual page 12

Table 3-125 Interrupt Status Register bit functions ..................................................................................... 3-124
Table 3-126 Results of access to the Interrupt Status Register .................................................................. 3-124
Table 3-127 FCSE PID Register bit functions ............................................................................................. 3-126
Table 3-128 Results of access to the FCSE PID Register .......................................................................... 3-126
Table 3-129 Context ID Register bit functions ............................................................................................ 3-128
Table 3-130 Results of access to the Context ID Register ......................................................................... 3-128
Table 3-131 Results of access to the thread and process ID registers ....................................................... 3-129
Table 3-132 Peripheral Port Memory Remap Register bit functions ........................................................... 3-131
Table 3-133 Results of access to the Peripheral Port Remap Register ...................................................... 3-131
Table 3-134 Secure User and Non-secure Access Validation Control Register bit functions ..................... 3-132
Table 3-135 Results of access to the Secure User and Non-secure Access Validation Control Register .. 3-133
Table 3-136 Performance Monitor Control Register bit functions ............................................................... 3-134
Table 3-137 Performance monitoring events .............................................................................................. 3-135
Table 3-138 Results of access to the Performance Monitor Control Register ............................................ 3-137
Table 3-139 Results of access to the Cycle Counter Register .................................................................... 3-138
Table 3-140 Results of access to the Count Register 0 .............................................................................. 3-139
Table 3-141 Results of access to the Count Register 1 .............................................................................. 3-140
Table 3-142 System validation counter register operations ........................................................................ 3-140
Table 3-143 Results of access to the System Validation Counter Register ................................................ 3-141
Table 3-144 System Validation Operations Register functions ................................................................... 3-142
Table 3-145 Results of access to the System Validation Operations Register ........................................... 3-143
Table 3-146 System Validation Cache Size Mask Register bit functions .................................................... 3-145
Table 3-147 Results of access to the System Validation Cache Size Mask Register ................................. 3-146
Table 3-148 TLB Lockdown Index Register bit functions ............................................................................ 3-149
Table 3-149 TLB Lockdown VA Register bit functions ................................................................................ 3-150
Table 3-150 TLB Lockdown PA Register bit functions ................................................................................ 3-150
Table 3-151 Access permissions APX and AP bit fields encoding ............................................................. 3-151
Table 3-152 TLB Lockdown Attributes Register bit functions ..................................................................... 3-151
Table 3-153 Results of access to the TLB lockdown access registers ....................................................... 3-152
Table 4-1 Unaligned access handling ......................................................................................................... 4-4
Table 4-2 Memory access types ............................................................................................................... 4-13
Table 4-3 Unalignment fault occurrence when access behavior is architecturally unpredictable ............. 4-14
Table 4-4 Legacy endianness using CP15 c1 ........................................................................................... 4-17
Table 4-5 Mixed-endian configuration ....................................................................................................... 4-19
Table 4-6 B bit, U bit, and EE bit settings ................................................................................................. 4-19
Table 6-1 Access permission bit encoding ................................................................................................ 6-12
Table 6-2 TEX field, and C and B bit encodings used in page table formats ............................................ 6-15
Table 6-3 Cache policy bits ....................................................................................................................... 6-16
Table 6-4 Inner and Outer cache policy implementation options .............................................................. 6-16
Table 6-5 Effect of remapping memory with TEX remap = 1 .................................................................... 6-17
Table 6-6 Values that remap the shareable attribute ................................................................................ 6-18
Table 6-7 Primary region type encoding ................................................................................................... 6-18
Table 6-8 Inner and outer region remap encoding .................................................................................... 6-18
Table 6-9 Memory attributes ..................................................................................................................... 6-20
Table 6-10 Memory region backwards compatibility ................................................................................... 6-26
Table 6-11 Fault Status Register encoding ................................................................................................. 6-34
Table 6-12 Summary of aborts .................................................................................................................... 6-35
Table 6-13 Translation table size ................................................................................................................ 6-43
Table 6-14 Access types from first-level descriptor bit values .................................................................... 6-45
Table 6-15 Access types from second-level descriptor bit values .............................................................. 6-47
Table 6-16 CP15 register functions ............................................................................................................. 6-53
Table 6-17 CP14 register functions ............................................................................................................. 6-54
Table 7-1 TCM configurations ..................................................................................................................... 7-7
Table 7-2 Access to Non-secure TCM ........................................................................................................ 7-8
Table 7-3 Access to Secure TCM ............................................................................................................... 7-8
Table 7-4 Summary of data accesses to TCM and caches ...................................................................... 7-14
Table 7-5 Summary of instruction accesses to TCM and caches ............................................................. 7-15
Table 8-1 AXI parameters for the level 2 interconnect interfaces ............................................................... 8-3
Table 8-2 AxLEN[3:0] encoding ................................................................................................................ 8-10
Table 8-3 AxSIZE[2:0] encoding ............................................................................................................... 8-11
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