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Operation
Store multiple
Swap
Change state
NOP-compatible
hints
Byte-reverse
Synchronization
primitives
Coprocessor
ARM DDI 0301H
ID012310
Stack operations
User registers
Increment before
Increment after
Decrement before
Decrement after
Word
Byte
Change processor state
Change processor mode
Change endianness
No Operation
Byte-reverse word
Byte-reverse halfword
Byte-reverse signed halfword
Load exclusive
Store exclusive
Load Byte Exclusive
Load Halfword Exclusive
Load Doubleword Exclusive
Store Byte Exclusive
Store Halfword Exclusive
Store Doubleword Exclusive
Clear Exclusive
Data operations
Move to ARM reg from coproc
Move to coproc from ARM reg
Move double to ARM reg
from coproc
Move double to coproc
from ARM reg
Load
Store
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Non-Confidential, Unrestricted Access
Table 1-7 ARM instruction set summary (continued)
Assembler
STM{cond}<a_mode4S> <Rn>{!}, <reglist>
STM{cond}<a_mode4S> <Rn>, <reglist>^
STM{cond}IB, <Rn>{!}, <reglist>{^}
STM{cond}IA, <Rn>{!}, <reglist>{^}
STM{cond}DB, <Rn>{!}, <reglist>{^}
STM{cond}DA, <Rn>{!}, <reglist>{^}
SWP{cond} <Rd>, <Rm>, [<Rn>]
SWP{cond}B <Rd>, <Rm>, [<Rn>]
CPS<effect> <iflags>{, <mode>}
CPS <mode>
SETEND <endian_specifier>
NOP{<cond>}
YIELD{<cond>}
REV{cond} <Rd>, <Rm>
REV16{cond} <Rd>, <Rm>
REVSH{cond} <Rd>, <Rm>
LDREX{cond} <Rd>, [<Rn>
]
STREX{cond} <Rd>, <Rm>, [<Rn>]
LDREXB{cond} <Rxf>, [<Rbase>]
LDREXH{cond} <Rd>, [<Rn>]
LDREXD{cond} <Rd>, [<Rn>]
STREXB{cond} <Rd>, <Rm>, [<Rn>]
STREXH{cond} <Rd>, <Rm>, [<Rn>]
STREXD{cond} <Rd>, <Rm>, [<Rn>]
CLREX
CDP{cond} <cp_num>, <op1>, <CRd>, <CRn>, <CRm>{, <op2>}
MRC{cond} <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}
MCR{cond} <cp_num>, <op1>, <Rd>, <CRn>, <CRm>{, <op2>}
MRRC{cond} <cp_num>, <op1>, <Rd>, <Rn>, <CRm>
MCRR{cond} <cp_num>, <op1>, <Rd>, <Rn>, <CRm>
LDC{cond} <cp_num>, <CRd>, <a_mode5>
STC{cond} <cp_num>, <CRd>, <a_mode5>
Introduction
1-36
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