ARM ARM1176JZF-S Technical Reference Manual

page of 759

/ 759
Contents
Table of Contents
Bookmarks

Table of Contents

Quick Links

ARM1176JZF-S

™

Revision: r0p7

Technical Reference Manual

ARM DDI 0301H (ID012310)

Table of Contents

Need help?

Do you have a question about the ARM1176JZF-S and is the answer not in the manual?

Questions and answers

Summary of Contents for ARM ARM1176JZF-S

Page 2: Change History
This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.
Page 3 Product Status The information in this document is final, that is for a developed product. Web Address http://www.arm.com ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 4: Table Of Contents
Introduction About the processor ....................1-2 Extensions to ARMv6 ....................1-3 TrustZone security extensions ................. 1-4 ARM1176JZF-S architecture with Jazelle technology ..........1-6 Components of the processor .................. 1-8 Power management ....................1-23 Configurable options ....................1-25 Pipeline stages ...................... 1-26 Typical pipeline operations ..................
Page 5 Data Read/Write Interface transfers ..............8-15 Peripheral Interface transfers ................8-37 Endianness ......................8-38 Locked access ....................... 8-39 Chapter 9 Clocking and Resets About clocking and resets ..................9-2 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 6 Debug sequences ....................14-29 14.9 Programming debug events ................. 14-40 14.10 Monitor debug-mode debugging ................14-42 Chapter 15 Trace Interface Port 15.1 About the ETM interface ..................15-2 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 7 Interrupting the VFP11 coprocessor ..............21-4 21.4 Forwarding ......................21-5 21.5 Hazards ......................... 21-6 21.6 Operation of the scoreboards ................21-7 21.7 Data hazards in full-compliance mode ..............21-13 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 8 Debug interface signals, including JTAG ............... A-14 ETM interface signals .................... A-15 Test signals ......................A-16 Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences About the differences between the ARM1136JF-S and ARM1176JZF-S processors ..Summary of differences ................... B-3 Appendix C Revisions Glossary ARM DDI 0301H Copyright ©...
Page 9 Summary of CP15 registers and operations ................3-14 Table 3-3 Summary of CP15 MCRR operations ..................3-19 Table 3-4 Main ID Register bit functions ....................3-20 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 10 Results of access to the Data Fault Status Register ..............3-66 Table 3-63 Instruction Fault Status Register bit functions ................3-67 Table 3-64 Results of access to the Instruction Fault Status Register ............3-67 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 11 Table 3-123 Monitor Vector Base Address Register bit functions ............... 3-123 Table 3-124 Results of access to the Monitor Vector Base Address Register ..........3-123 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 12 Summary of instruction accesses to TCM and caches ............. 7-15 Table 8-1 AXI parameters for the level 2 interconnect interfaces ............... 8-3 Table 8-2 AxLEN[3:0] encoding ........................ 8-10 Table 8-3 AxSIZE[2:0] encoding ....................... 8-11 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 13 Cacheable Write-Through or Noncacheable STM8 to word 1, 2, 3, 4, 5, 6, or 7 ...... 8-32 Table 8-62 Cacheable Write-Through or Noncacheable STM9 ..............8-32 Table 8-63 Cacheable Write-Through or Noncacheable STM10 ..............8-33 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. xiii ID012310 Non-Confidential, Unrestricted Access...
Page 14 Data Processing Instruction cycle timing behavior if destination is the PC ....... 16-7 Table 16-6 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior ........16-9 Table 16-7 ARMv6 media data-processing instructions cycle timing behavior ......... 16-10 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 15 Table 21-12 FLDM-FLDS-FADDS resource hazard ................... 21-18 Table 21-13 FLDM-short vector FMULS resource hazard ................21-18 Table 21-14 Short vector FDIVS-FADDS resource hazard ................. 21-19 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 16 Test signals ..........................A-16 Table B-1 TCM for ARM1176JZF-S processors ..................B-6 Table B-2 CP15 c15 features common to ARM1136JF-S and ARM1176JZF-S processors ...... B-8 Table B-3 CP15 c15 only found in ARM1136JF-S processors ..............B-9 Table C-1 Differences between issue G and issue H .................. C-1 ARM DDI 0301H Copyright ©...
Page 17 Processor core register set showing banked registers ............. 2-21 Figure 2-8 Register organization in Thumb state ..................2-22 Figure 2-9 ARM state and Thumb state registers relationship ..............2-23 Figure 2-10 Program status register ......................2-24 Figure 2-11 LDREXB instruction ........................2-30 Figure 2-12 STREXB instructions ........................
Page 18 DMA Channel Number Register format .................. 3-109 Figure 3-62 DMA Control Register format ....................3-112 Figure 3-63 DMA Channel Status Register format ..................3-117 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. xviii ID012310 Non-Confidential, Unrestricted Access...
Page 19 Processor synchronization with IEM ................... 9-6 Figure 9-5 Read latency with IEM ........................ 9-8 Figure 9-6 Power-on reset .......................... 9-10 Figure 10-1 IEM structure ..........................10-8 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 20 Floating-Point Exception Register ................... 20-17 Figure 20-8 Media and VFP Feature Register 0 format ................20-19 Figure 20-9 Media and VFP Feature Register 1 format ................20-20 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 21 This preface introduces the ARM1176JZF-S Technical Reference Manual (TRM). It contains the ™ following sections: • About this book on page xxii • Feedback on page xxvi. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 22: Preface
Preface About this book This book is for ARM1176JZF-S processor. In this manual the generic term processor means the ARM1176JZF-S processor. Product revision status The rnpn identifier indicates the revision status of the product described in this book, where: Identifies the major revision of the product.
Page 23 Appendix A Signal Descriptions Read this for a description of the processor signals. Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences Read this for a summary of the differences between the ARM1136JF-S ™ ARM1176JZF-S processors.
Page 24: Key To Timing Diagram Conventions
HIGH to LOW Transient HIGH/LOW to HIGH Bus stable Bus to high impedance Bus change High impedance to stable bus Key to timing diagram conventions ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. xxiv ID012310 Non-Confidential, Unrestricted Access...
Page 25: Other Publications
• ARM Architecture Reference Manual (ARM DDI 0406) Note The ARM DDI 0406 edition of the ARM Architecture Reference Manual (the ARM ARM) incorporates the supplements to the previous ARM ARM, including the Security Extensions supplement. •...
Page 26: Feedback
Preface Feedback ARM welcomes feedback on this product and its documentation. Feedback on this product If you have any comments or suggestions about this product, contact your supplier and give: • The product name. • The product revision or version.
Page 27 Chapter 1 Introduction This chapter introduces the ARM1176JZF-S processor and its features. It contains the following sections: • About the processor on page 1-2 • Extensions to ARMv6 on page 1-3 • TrustZone security extensions on page 1-4 • ARM1176JZF-S architecture with Jazelle technology on page 1-6 •...
Page 28: Chapter 1 Introduction
Introduction About the processor The ARM1176JZF-S processor incorporates an integer core that implements the ARM11 ARM ™ architecture v6. It supports the ARM and Thumb instruction sets, Jazelle technology to enable direct execution of Java bytecodes, and a range of SIMD DSP instructions that operate on 16-bit or 8-bit data values in 32-bit registers.
Page 29: Extensions To Armv6
CP15 Register 1. • Revised use of AP bits. In the ARM1176JZF-S processor the APX and AP[1:0] encoding b111 is Privileged or User mode read only access. AP[0] indicates an abort type, Access Bit fault, when CP15 c1[29] is 1.
Page 30: Trustzone Security Extensions
The ARM1176JZF-S processor supports TrustZone security extensions to provide a secure environment for software. This section summarizes processor elements that TrustZone uses. For details of TrustZone, see the ARM Architecture Reference Manual.
Page 31 BRESP[1:0] Write response signal, see AXI interface signals on page A-7. ETMIASECCTL[1:0] and ETMCPSECCTL[1:0] TrustZone information for tracing, see Secure control bus on page 15-4. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 32: Arm1176Jzf-S Architecture With Jazelle Technology
• the 8-bit Java bytecodes used in Jazelle state. For details of both the ARM and Thumb instruction sets, see the ARM Architecture Reference Manual. For full details of the ARM1176JZF-S Java instruction set, see the Jazelle V1 Architecture Reference Manual.
Page 33 Software execution Bytecodes that are too complex to execute directly in hardware are executed in software. An ARM register is used to access a table of exception handlers to handle these particular bytecodes. A complete list of the ARM1176JZF-S processor-supported Java bytecodes and their corresponding hardware or software instructions is in the Jazelle V1 Architecture Reference Manual.
Page 34: Components Of The Processor
Figure 1-1 ARM1176JZF-S processor block diagram 1.5.1 Integer core The ARM1176JZF-S processor is built around the ARM11 integer core. It is an implementation of the ARMv6 architecture, that runs the ARM, Thumb, and Java instruction sets. The processor ™ contains EmbeddedICE-RT logic and a JTAG debug interface to enable hardware debuggers to communicate with the processor.
Page 35: Conditional Execution
Only load, store, and swap instructions can access data from memory. Conditional execution The processor conditionally executes nearly all ARM instructions. You can decide if the condition code flags, Negative, Zero, Carry, and Overflow, are updated according to their result.
Page 36 Introduction • Secure Monitor. Thumb instruction set The Thumb instruction set contains a subset of the most commonly-used 32-bit ARM instructions encoded into 16-bit wide opcodes. This reduces the amount of memory required for instruction storage. DSP instructions The DSP extensions to the ARM instruction set provide: •...
Page 37: Figure
The core uses both static and dynamic branch prediction. All branches are predicted where the target address is an immediate address, or fixed-offset PC-relative address. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-11 ID012310 Non-Confidential, Unrestricted Access...
Page 38 Data cache misses that are non-blocking. The processor supports up to three outstanding data cache misses. • Streaming of sequential data from LDM and LDRD operations, and sequential instruction fetches. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-12 ID012310 Non-Confidential, Unrestricted Access...
Page 39: Table 1-1 Tcm Configurations
So, for example, if you configure an ITCM size of 16KB you get two ITCMs, each of size 8KB. Table 1-1 lists all possible TCM configurations. See Configurable options on page 1-25 for more information about configuring your ARM1176JZF-S implementation. Table 1-1 TCM configurations Configured TCM size...
Page 40: Figure
The MMU includes a 4KB page mapping size to enable a smaller RAM and ROM footprint for embedded systems and operating systems such as WindowsCE that have many small mapped objects. The ARM1176JZF-S processor implements the Fast Context Switch Extension (FCSE) and high vectors extension that are required to run Microsoft WindowsCE.
Page 41 This coprocessor provides a standard mechanism for configuring the level one memory system, and also provides functions such as memory barrier instructions. See System control on page 1-21 for more details. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-15 ID012310 Non-Confidential, Unrestricted Access...
Page 42 This means the core can share data with big-endian systems, and improves the way the core manages certain types of data. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-16 ID012310 Non-Confidential, Unrestricted Access...
Page 43: Coprocessor Interface
Accesses to these memory regions are routed to the peripheral port instead of to the data read-write ports. See Chapter 8 Level Two Interface for more details. 1.5.6 Coprocessor interface The ARM1176JZF-S processor connects to external coprocessors through the coprocessor interface. This interface supports all ARM coprocessor instructions: • • LDCL •...
Page 44 You can perform internal diagnostics on a closed system where a JTAG port is not normally brought out. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-18 ID012310 Non-Confidential, Unrestricted Access...
Page 45 The VFP coprocessor supports floating point arithmetic operations and is a functional block within the ARM1176JZF-S processor. The VFP coprocessor is mapped as coprocessor numbers 10 and 11. Software can determine whether the VFP is present by the use of the Coprocessor Access Control Register.
Page 46: Table 1-2 Double-Precision Vfp Operations
The following operations are not directly supported by the VFP: • remainder • binary (decimal) conversions • direct comparisons between single and double-precision values. These are normally implemented as C library functions. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-20 ID012310 Non-Confidential, Unrestricted Access...
Page 47 Vectored Interrupt Controller port The core has a dedicated port that enables an external interrupt controller, such as the ARM Vectored Interrupt Controller (VIC), to supply a vector address along with an interrupt request (IRQ) signal.
Page 48 With TrustZone, in Non-secure state, specifying Secure Monitor mode in the field of the <mode> instruction causes the processor to take the Undefined exception. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-22 ID012310 Non-Confidential, Unrestricted Access...
Page 49: Power Management
Extensive use of gated clocks and gates to disable inputs to unused functional blocks. Because of this, only the logic actively in use to perform a calculation consumes any dynamic power. • Optionally supports IEM. The ARM1176JZF-S is separated into three different blocks to support three different power domains: — all the RAMS the core logic that is clocked by CLKIN and FREECLKIN —...
Page 50 RAM blocks to include an input clamp • implement separate power domains. For full implementation of dormant mode see ARM1176JZF-S and ARM1176JZ-S Implementation Guide. For more details of power management features see Chapter 10 Power Control. ARM DDI 0301H Copyright ©...
Page 51: Configurable Options
Number of TCM blocks depends only on the size of the TCM RAM. In addition, the form of the BIST solution for the RAM blocks in the ARM1176JZF-S design is determined when the processor is implemented. For details, see the ARM11 Memory Built-In Self Test Controller Technical Reference Manual.
Page 52: Pipeline Stages
Second stage of data cache access. WBls Write back of data from the Load Store Unit. By overlapping the various stages of operation, the ARM1176JZF-S processor maximizes the clock rate achievable to execute each instruction. It delivers a throughput approaching one instruction for each cycle.
Page 53 The Execute, Memory, and Write stages can contain a predicted branch, an ALU or multiply instruction, a load/store multiple instruction, and a coprocessor instruction in parallel execution. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-27 ID012310...
Page 54: Typical Pipeline Operations
The MUL instruction progresses to MAC2 and MAC3 where it passes through the second half of the array once to produce the final result. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-28 ID012310 Non-Confidential, Unrestricted Access...
Page 55: Figure 1-5 Typical Multiply Operation
Common decode pipeline WBls Load/store Not used Not used Not used Not used pipeline Hit under Not used miss Figure 1-5 Typical multiply operation ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-29 ID012310 Non-Confidential, Unrestricted Access...
Page 56: Figure 1-6 Progression Of An Ldr/Str Operation
Figure 1-8 on page 1-31 shows the progression of an LDR that misses. When the LDR is in the HUM buffers, other instructions, including independent loads that hit in the cache, can run under ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-30 ID012310...
Page 57: Figure 1-8 Progression Of An Ldr That Misses
Load miss Figure 1-8 Progression of an LDR that misses See Chapter 16 Cycle Timings and Interlock Behavior for details of instruction cycle timings. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-31 ID012310 Non-Confidential, Unrestricted Access...
Page 58: Arm1176Jzf-S Instruction Set Summary
Table 1-6 lists a key to the ARM and Thumb instruction set tables. The ARM1176JZF-S processor implements the ARM architecture v6 with ARM Jazelle technology. For a description of the ARM and Thumb instruction sets, see the ARM Architecture Reference Manual. Contact ARM Limited for complete descriptions of all instruction sets.
Page 59: Table 1-7 Arm Instruction Set Summary
0 to 31. • must be in the range 1 to 32. ASR #N 1.10.1 Extended ARM instruction set summary Table 1-7 summarizes the extended ARM instruction set. Table 1-7 ARM instruction set summary Operation Assembler Arithmetic ADD{cond}{S} <Rd>, <Rn>, <operand2>...
Page 60 Branch and exchange BX{cond} <Rm> Branch, link and exchange BLX <label> Branch, link and exchange BLX{cond} <Rm> Branch and exchange to Jazelle BXJ{cond} <Rm> state ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-34 ID012310 Non-Confidential, Unrestricted Access...
Page 61 STR{cond}B <Rd>, <a_mode2> Byte with User mode privilege STR{cond}BT <Rd>, <a_mode2P> Halfword STR{cond}H <Rd>, <a_mode3> Doubleword STR{cond}D <Rd>, <a_mode3> Store return state SRS<a_mode4> <mode>{!} ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-35 ID012310 Non-Confidential, Unrestricted Access...
Page 62 Move double to coproc MCRR{cond} <cp_num>, <op1>, <Rd>, <Rn>, <CRm> from ARM reg Load LDC{cond} <cp_num>, <CRd>, <a_mode5> Store STC{cond} <cp_num>, <CRd>, <a_mode5> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-36 ID012310 Non-Confidential, Unrestricted Access...
Page 63 16 - high 16, halved Signed high 16 - low 16, SSUBADDX{cond} <Rd>, <Rn>, <Rm> low 16 + high 16, set GE flags ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-37 ID012310 Non-Confidential, Unrestricted Access...
Page 64: Table
Four unsigned 8 - 8, halved UHSUB8{cond} <Rd>, <Rn>, <Rm> Sum of absolute differences USAD8{cond} <Rd>, <Rm>, <Rs> Sum of absolute differences and USADA8{cond} <Rd>, <Rm>, <Rs>, <Rn> accumulate ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-38 ID012310 Non-Confidential, Unrestricted Access...
Page 65 32 - truncated high 16 (32 x 32) SMMLS{cond} <Rd>, <Rm>, <Rs>, <Rn> 32 -rounded high 16 (32 x 32) SMMLSR{cond} <Rd>, <Rm>, <Rs>, <Rn> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-39 ID012310 Non-Confidential, Unrestricted Access...
Page 66 [<Rn>, +/-<Rm>] Scaled register offset [<Rn>, +/-<Rm>, LSL #<immed_5>] [<Rn>, +/-<Rm>, LSR #<immed_5>] [<Rn>, +/-<Rm>, ASR #<immed_5>] [<Rn>, +/-<Rm>, ROR #<immed_5>] [<Rn>, +/-<Rm>, RRX] ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-40 ID012310 Non-Confidential, Unrestricted Access...
Page 67: Table 1-8 Addressing Mode 2
[<Rn>], +/-<Rm> Scaled register offset [<Rn>], +/-<Rm>, LSL #<immed_5> [<Rn>], +/-<Rm>, LSR #<immed_5> [<Rn>], +/-<Rm>, ASR #<immed_5> [<Rn>], +/-<Rm>, ROR #<immed_5> [<Rn>], +/-<Rm>, RRX ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-41 ID012310 Non-Confidential, Unrestricted Access...
Page 68: Addressing Mode 3
Table 1-12 summarizes addressing mode 5. Table 1-12 Addressing mode 5 Addressing mode Assembler Immediate offset [<Rn>, #+/-<immed_8*4>] Immediate pre-indexed [<Rn>, #+/-<immed_8*4>]! Immediate pre-indexed [<Rn>], #+/-<immed_8*4> Unindexed [<Rn>], <option> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-42 ID012310 Non-Confidential, Unrestricted Access...
Page 69: Table 1-13 Operand2
Not equal Unsigned higher or same, carry set HS/CS Unsigned lower, carry clear LO/CC Negative, minus Positive or zero, plus Overflow No overflow Unsigned higher ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-43 ID012310 Non-Confidential, Unrestricted Access...
Page 70: Table 1-16 Thumb Instruction Set Summary
SUB <Rd>, <Rn>, #<immed_3> Subtract immediate SUB <Rd>, #<immed_8> Subtract SUB <Rd>, <Rn>, <Rm> Subtract immediate from SP SUB SP, #<immed_7*4> Subtract with carry SBC <Rd>, <Rm> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-44 ID012310 Non-Confidential, Unrestricted Access...
Page 71 LDR <Rd>, [<Rn>, #<immed_5*4>] Halfword LDRH <Rd>, [<Rn>, #<immed_5*2>] Byte LDRB <Rd>, [<Rn>, #<immed_5>] With register offset Word LDR <Rd>, [<Rn>, <Rm>] Halfword LDRH <Rd>, [<Rn>, <Rm>] ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-45 ID012310 Non-Confidential, Unrestricted Access...
Page 72 Sign extend 16 to 32 SXTH<Rd>, <Rm> Sign extend 8 to 32 SXTB<Rd>, <Rm> Zero extend 16 to 32 UXTH<Rd>, <Rm> Zero extend 8 to 32 UXTB<Rd>, <Rm> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 1-46 ID012310 Non-Confidential, Unrestricted Access...
Page 73: Product Revisions
IEM. See Intelligent Energy Management on page 10-7. • The architectural clock gating scheme for the generation of clock dedicated to the RAMs has been changed. For more information see the description of the RAM interface implementation in the ARM1176JZF-S ™ ARM1176JZ-S ™...
Page 74 • The program status registers on page 2-24 • Additional instructions on page 2-30 • Exceptions on page 2-36 • Software considerations on page 2-59. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 75: Chapter 2 Programmer's Model
The architecture includes the 32-bit ARM instruction set, 16-bit Thumb instruction set, and the 8-bit Java instruction set. For details of both the ARM and Thumb instruction sets, see the ARM Architecture Reference Manual. For the Java instruction set see the Jazelle V1 Architecture Reference Manual.
Page 76: Secure World And Non-Secure World Operation With Trustzone
• TrustZone model • How the Secure model works on page 2-4. For more details on TrustZone and the ARM architecture, see the ARM Architecture Reference Manual. 2.2.1 TrustZone model The basis of the TrustZone model is that the computing environment splits into two isolated worlds, the Secure world and the Non-secure world, with no leakage of Secure data to the Non-secure world.
Page 77 NS bit, it is strongly recommended that you only use the Secure Monitor to change the NS bit. See the ARM Architecture Reference Manual for more information. A Secure Monitor Call (SMC) is used to enter the Secure Monitor mode and perform a Secure Monitor kernel service call.
Page 78 Programmer’s Model Execute a MOVS, SUBS or RFE. All ARM implementations ensure that the processor can not execute the prefetched instructions that follow MOVS, SUBS, or equivalents, with Secure access permissions. It is strongly recommended that you do not use an MSR instruction to switch from the Secure to the Non-secure world.
Page 79: Figure 2-2 Memory In The Secure And Non-Secure Worlds
AxPROT[1] S prot S prot Non- Master secure Arbiter Decoder External Secure peripheral slave memory slave Figure 2-2 Memory in the Secure and Non-secure worlds ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 80: Figure 2-3 Memory Partition In The Secure And Non-Secure Worlds
1MB sections Non-secure SDRAM Secure level 2 Secure descriptors peripherals Non-secure peripherals 4KB small pages Figure 2-3 Memory partition in the Secure and Non-secure worlds ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 81: Figure
Secure peripherals by checking the AxPROT[1] signal and generating an error response if a Non-secure access attempts to read or write a Secure register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 82: Table 2-1 Write Access Behavior For System Control Processor Registers
MCR p15, 0, Rd, c3, c0, 0 Register Data TCM Non-secure Control Secure Monitor or Privileged when NS=0 MCR p15, 0, Rd, c9, c1, 2 Access Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 83 SoC, and must not appear outside the chip. Table 2-2 on page 2-11 lists the signals that appear on the Secure Monitor bus SECMONBUS. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-10 ID012310 Non-Confidential, Unrestricted Access...
Page 84: Table 2-2 Secure Monitor Bus Signals
SECMONBUS output pins except bits [24:23] and bits [2:0]. nPORESETIN resets the output pins for bits [24:23] and bits [2:0]. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-11 ID012310 Non-Confidential, Unrestricted Access...
Page 85: Processor Operating States
Switching state You can switch the operating state of the processor between: • ARM state and Thumb state using the BX and BLX instructions, and loads to the PC. The ARM Architecture Reference Manual describes the switching state. • ARM state and Jazelle state using the BXJ instruction.
Page 86: Instruction Length
• 32 bits long, in ARM state • 16 bits long, in Thumb state • variable length, multiples of 8 bits, in Jazelle state. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-13 ID012310 Non-Confidential, Unrestricted Access...
Page 87: Data Types
Unaligned and Mixed-endian Data Access Support. Note You cannot use LDRD, LDM, LDC, STRD, STM, or STC instructions to access 32-bit quantities if they are unaligned. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-14 ID012310 Non-Confidential, Unrestricted Access...
Page 88: Memory Formats
• Least significant byte is at lowest address • Word is addressed by byte address of least significant byte Figure 2-5 Little-endian addresses of bytes within words ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-15 ID012310 Non-Confidential, Unrestricted Access...
Page 89: Addresses In A Processor System
The external access is always Non-secure when the core is in Non-secure world. In Secure world, the external access is Secure or Non-secure according to the NS attribute value in the selected descriptor. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-16 ID012310 Non-Confidential, Unrestricted Access...
Page 90: Operating Modes
Operating modes In all states there are eight modes of operation: • User mode is the usual ARM program execution state, and is used for executing most application programs • Fast interrupt (FIQ) mode is used for handling fast interrupts •...
Page 91: Registers
2.9.1 The ARM state core register set In ARM state, 16 general registers and one or two status registers are accessible at any time. In privileged modes, mode-specific banked registers become available. Figure 2-6 on page 2-20 shows the registers that are available in each mode.
Page 92: Table 2-5 Register Mode Identifiers
The Secure Monitor, Supervisor, Abort, IRQ, and Undefined modes each have alternative mode-specific registers mapped to R13 and R14, permitting a private stack pointer and link register for each mode. Figure 2-6 on page 2-20 shows the ARM state registers. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved.
Page 93: Figure 2-6 Register Organization In Arm State
SPSR_mon SPSR_abt SPSR_irq = banked register Figure 2-6 Register organization in ARM state Figure 2-7 on page 2-21 shows an alternative view of the ARM registers. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-20 ID012310 Non-Confidential, Unrestricted Access...
Page 94: Figure 2-7 Processor Core Register Set Showing Banked Registers
Figure 2-7 Processor core register set showing banked registers 2.9.2 The Thumb state core register set The Thumb state core register set is a subset of the ARM state set. The programmer has direct access to: • eight general registers, R0–R7. For details of high register access in Thumb state see Accessing high registers in Thumb state on page 2-22 •...
Page 95: Figure 2-8 Register Organization In Thumb State
R0–R7, to a high register, and from a high register to a low register. The CMP instruction enables you to compare high register values with low register values. The ADD instruction enables you to add high register values to low register values. For more details, see the ARM Architecture Reference Manual.
Page 96: Figure 2-9 Arm State And Thumb State Registers Relationship
Program Counter (R15) CPSR CPSR SPSR SPSR Figure 2-9 ARM state and Thumb state registers relationship Note Registers R0–R7 are known as the low registers. Registers R8–R15 are known as the high registers. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved.
Page 97: The Program Status Registers
MSR and LDM instructions. The processor tests these flags to determine whether to execute an instruction. In ARM state, most instructions can execute conditionally on the state of the N, Z, C, and V bits. The exceptions are: •...
Page 98 Thumb-aware processor. That is, the next instruction executed causes entry to the Undefined Instruction exception. Entry to the exception handler causes the processor to re-enter ARM state, and the handler can detect that this was the cause of the exception because J and T are both set in SPSR_und.
Page 99: Table 2-6 Ge[3:0] Settings
Note • For unsigned operations, the GE bits are determined by the usual ARM rules for carries out of unsigned additions and subtractions, and so are carry-out bits. • For signed operations, the rules for setting the GE bits are chosen so that they have the same sort of greater than or equal functionality as for unsigned operations.
Page 100 • when the T bit is set, the processor is executing in Thumb state • when the T bit is clear, the processor is executing in ARM state, or Jazelle state depending on the J bit. Note Never use an MSR instruction to force a change to the state of the T bit in the CPSR. If an MSR instruction does try to modify this bit the result is architecturally Unpredictable.
Page 101: Table 2-7 Psr Mode Bit Values
In previous architecture versions, MSR instructions can modify the flags byte, bits [31:24], of the CPSR in any mode, but the other three bytes are only modifiable in privileged modes. After the introduction of ARM architecture v6, however, each CPSR bit falls into one of the following categories: •...
Page 102 You must ensure that your program does not rely on reserved bits containing specific values because future processors might use some or all of the reserved bits. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-29 ID012310 Non-Confidential, Unrestricted Access...
Page 103: Additional Instructions
Programmer’s Model 2.11 Additional instructions To support extensions to ARMv6, the ARM1176JZF-S processor includes these instructions in addition to those in the ARMv6 and TrustZone architectures: • Load Register Exclusive instructions, see LDREXB, LDREXH on page 2-31, and LDREXD on page 2-33 •...
Page 104: Figure 2-13 Ldrexh Instruction
Figure 2-13 LDREXH instruction Syntax LDREXH{<cond>} <Rd>, [<Rn>] Operation if ConditionPassed(cond) then processor_id = ExecutingProcessor() Rd = Memory[Rn,2] if Shared(Rn) ==1 then physical_address=TLB(Rn) MarkExclusiveGlobal(physical_address,processor_id,2) MarkExclusiveLocal(processor_id) ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-31 ID012310 Non-Confidential, Unrestricted Access...
Page 105: Figure 2-14 Strexh Instruction
The operands are considered as two words, that load or store to consecutive word-addressed locations in memory. • Register restrictions are the same as LDRD and STRD. For STRD in ARM state, the registers Rm and R(m+1) provide the value that is stored, where m is an even number. •...
Page 106: Figure 2-15 Ldrexd Instruction
Memory[Rn+4,4] = R(m+1) Rd = 0 ClearByAddress(physical_address,8) else Rd =1 else Memory[Rn,4] = Rm Memory[Rn+4,4] = R(m+1) Rd = 0 else Rd = 1 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-33 ID012310 Non-Confidential, Unrestricted Access...
Page 107: Figure 2-17 Clrex Instruction
== 0x1: the instruction is YIELD For all other values, RESERVED, the instruction behaves like NOP. The true NOP for ARM state is equivalent to an MSR to the CPSR with the immed_value redefined as the hint field and no bytes selected. The instruction is fully architecturally defined, with all encodings assigned.
Page 108 The instruction acts as a NOP irrespective of whether the condition passes or fails, effectively the ALWAYS condition. Do not use RESERVED values in software. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-35 ID012310 Non-Confidential, Unrestricted Access...
Page 109: Exceptions
The addressing mode used is a version of an ARM addressing mode, modified to assume a {R14,SPSR} register list rather than using a list specified by a bit mask in the instruction. For more information see the ARM Architecture Reference Manual.
Page 110: Table 2-8 Exception Entry And Exit
This instruction loads the PC and CPSR from sequential addresses. This is used to return from an exception that has had its return state saved using the SRS instruction, see Store Return State (SRS) on page 2-36, and again uses a version of an ARM addressing mode, modified to assume a {PC,CPSR} register list.
Page 111 Exceptions are always entered, handled, and exited in ARM state. When the processor is in Thumb state or Jazelle state and an exception occurs, the switch to ARM state takes place automatically when the exception vector address is loaded into the PC.
Page 112 It is the output of this register that is used by the processor control logic. Irrespective of whether exception entry is from ARM state, Thumb state, or Jazelle state, an FIQ handler returns from the interrupt by executing: SUBS PC,R14_fiq,#4 You can disable FIQ exceptions within a privileged mode by setting the CPSR F flag.
Page 113 The instructions that this rule currently applies to are: • ARM instructions LDC, all forms of LDM, LDRD, STC, all forms of STM, STRD, and unaligned LDR, STR, LDRH, and STRH •...
Page 114 The corresponding exception priority structure is as follows, from highest to lowest priority: FIQ1, highest priority FIQ FIQ2 FIQm, lowest priority FIQ Data Abort Prefetch Abort Undefined instruction IRQ1, highest priority IRQ IRQ2 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-41 ID012310 Non-Confidential, Unrestricted Access...
Page 115 FIQ entry sequence executed, updating R14_fiq, SPSR_fiq, PC, and CPSR. FIQ handler executes to completion and returns. Data Abort handler executes to completion and returns. For more information see the ARM Architecture Reference Manual. Stack and register usage is: •...
Page 116 FIQ vector, and the changeover to a different stack occurs much more smoothly. The code is: FIQ1handler ... Include code to process the interrupt ... ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-43 ID012310 Non-Confidential, Unrestricted Access...
Page 117 FIQ handler before it can do any useful work. That is, it increases the effective FIQ latency by a similar number of cycles. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-44 ID012310...
Page 118 3-52, the core branches to Secure Monitor mode in the same way as it does for all other external aborts. Prefetch Abort This is signaled with the Instruction as it enters the pipeline Decode stage. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-45 ID012310 Non-Confidential, Unrestricted Access...
Page 119 This removes the requirement for the Data Abort handler to unwind any base register update, that might have been specified by the aborted instruction. This simplifies the software Data Abort handler. See ARM Architecture Reference Manual for more details.
Page 120 Secure Monitor code. For more details on SMC and the Secure Monitor, see The NS bit and Secure Monitor mode on page 2-4. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-47 ID012310...
Page 121: Exception Vectors
When an instruction is encountered that neither the processor, nor any coprocessor in the system, can handle the processor takes the undefined instruction trap. Software can use this mechanism to extend the ARM instruction set by emulating undefined coprocessor instructions. After emulating the failed instruction, the trap handler executes the following instruction,...
Page 122 SPSR_svc = UNPREDICTABLE value CPSR [4:0] = 0b10011 /* Enter supervisor mode */ CPSR [5] = 0 /* Execute in ARM state */ CPSR [6] = 1 /* Disable fast interrupts */ CPSR [7] = 1 /* Disable interrupts */...
Page 123 SPSR_mon = CPSR CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */ CPSR [5] = 0 /* Execute in ARM state */ CPSR [6] = 1 /* Disable fast interrupts */ CPSR [7] = 1 /* Disable interrupts */...
Page 124 Programmer’s Model CPSR [5] = 0 /* Execute in ARM state */ CPSR [6] = 1 /* Disable fast interrupts */ CPSR [7] = 1 /* Disable interrupts */ CPSR [8] = 1 /* Disable imprecise aborts */ CPSR [9] = Secure EE-bit /* store value of secure Ctrl Reg bit[25] */...
Page 125 Programmer’s Model CPSR [4:0] = 0b10010 /* Enter IRQ mode */ CPSR [5] = 0 /* Execute in ARM state */ CPSR [7] = 1 /* Disable interrupts */ If SCR[5]=1 (bit AW) CPSR [8] = 1 /* Disable imprecise aborts */...
Page 126 SPSR_mon = CPSR CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */ CPSR [5] = 0 /* Execute in ARM state */ CPSR [6] = 1 /* Disable fast interrupts */ CPSR [7] = 1 /* Disable interrupts */...
Page 127 SPSR_und = CPSR CPSR [4:0] = 0b11011 /* Enter undefined Instruction mode */ CPSR [5] = 0 /* Execute in ARM state */ CPSR [7] = 1 /* Disable interrupts */ CPSR [9] = Secure EE-bit /* store value of secure Control Reg[25] */...
Page 128 R14_abt = address of the aborted instruction + 4 SPSR_abt = CPSR CPSR [4:0] = 0b10111 /* Enter abort mode */ CPSR [5] = 0 /* Execute in ARM state */ CPSR [7] = 1 /* Disable interrupts */ CPSR [8] = 1 /* Disable imprecise aborts */...
Page 129 SPSR_mon = CPSR CPSR [4:0] = 0b10110 /* Enter Secure Monitor mode */ CPSR [5] = 0 /* Execute in ARM state */ CPSR [6] = 1 /* Disable fast interrupts */ CPSR [7] = 1 /* Disable interrupts */...
Page 130: Table 2-9 Exception Priorities
SPSR_und = CPSR CPSR [4:0] = 0b11011 /* Enter undefined instruction mode */ CPSR [5] = 0 /* Execute in ARM state */ CPSR [7] = 1 /* Disable interrupts */ CPSR [9] = Secure EE-bit /* store value of secure Control Reg[25] */...
Page 131 If the data abort is a precise external abort and bit 3 (EA) of SCR is set, the processor enters Secure Monitor mode where aborts and FIQs are disabled automatically. Therefore, the processor does not proceed to FIQ vector immediately afterwards. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-58 ID012310 Non-Confidential, Unrestricted Access...
Page 132: Software Considerations
For details of the WFI operation see c7, Cache operations on page 3-69. Note In the ARM1176 instruction set, is a valid instruction but is treated as a NOP. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 2-59 ID012310 Non-Confidential, Unrestricted Access...
Page 133: Chapter 3 System Control Coprocessor
It contains the following sections: • About the system control coprocessor on page 3-2 • System control processor registers on page 3-13. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 134: About The System Control Coprocessor
System control processor registers on page 3-13. The purpose of the system control coprocessor, CP15, is to control and provide status information for the functions implemented in the ARM1176JZF-S processor. The main functions of the system control coprocessor are: •...
Page 135: Table 3-1 System Control Coprocessor Register Functions
FCSE PID Register on page 3-126 Thread And Process ID c13, Thread and process ID registers on page 3-129 TLB Lockdown Access c15, TLB lockdown access registers on page 3-149 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 136 Cycle Counter Register on page 3-137 monitor Count Register 0 c15, Count Register 0 on page 3-138 Count Register 1 c15, Count Register 1 on page 3-139 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 137: Figure 3-1 System Control And Configuration Registers
To use the system control and configuration registers you read or write individual registers that make up the group, see Use of the system control coprocessor on page 3-12. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 138 The MMU control and configuration registers consist of one 32-bit read-only register, one 32-bit write-only register, and 22 32-bit read/write registers. Figure 3-2 on page 3-7 shows the arrangement of registers in this functional group. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 139: Figure 3-2 Mmu Control And Configuration Registers
The cache control and configuration registers consist of one 32-bit read only register and four 32-bit read/write registers. Figure 3-3 on page 3-8 shows the arrangement of the registers in this functional group. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 140: Figure 3-3 Cache Control And Configuration Registers
The cache debug registers consist of two 32-bit read/write registers. Figure 3-5 on page 3-9 shows the arrangement of registers in this functional group. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 141: Figure 3-5 Cache Master Valid Registers
DMA User Accessibility Register. If DMA control registers attempt to execute a privileged operation in User mode the processor takes an Undefined instruction trap. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 142: Figure 3-7 System Performance Monitor Registers
The system validation registers extend the use of the system performance monitor registers to provide some functions for validation and must not be used for other purposes. The system validation registers schedule and clear: • resets ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-10 ID012310 Non-Confidential, Unrestricted Access...
Page 143: Figure 3-8 System Validation Registers
TCMs to make their size appear different to the processor. You can use this in validation by simulation, but you must not use it in a manufactured device because it can corrupt correct operation of the processor. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-11 ID012310 Non-Confidential, Unrestricted Access...
Page 144: Figure 3-9 Cp15 Mrc And Mcr Bit Pattern
In all cases, reading from or writing any data values to any CP15 registers, including those fields specified as Unpredictable (UNP), Should Be One (SBO), or Should Be Zero (SBZ), does not cause any physical damage to the chip. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-12 ID012310 Non-Confidential, Unrestricted Access...
Page 145: System Control Processor Registers
R/W, read/write access in privileged modes only WO, write-only access — — WO, write-only access in privileged modes only — X, access depends on another register or external signal. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-13 ID012310 Non-Confidential, Unrestricted Access...
Page 146: Table 3-2 Summary Of Cp15 Registers And Operations
0x00000007 Coprocessor Access Control page 3-51 0x00000000 Secure Configuration page 3-52 0x00000000 Secure Debug Enable page 3-54 0x00000000 Non-Secure Access Control page 3-55 0x00000000 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-14 ID012310 Non-Confidential, Unrestricted Access...
Page 147 Invalidate Both Caches page 3-71 VA to PA translation in the page 3-82 current world VA to PA translation in the page 3-83 other world ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-15 ID012310 Non-Confidential, Unrestricted Access...
Page 148 3-86 unlocked entries Invalidate unified TLB entry WO, B page 3-86 by MVA Invalidate unified TLB entry WO, B page 3-86 on ASID match ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-16 ID012310 Non-Confidential, Unrestricted Access...
Page 149 Secure or Non-secure Vector R/W, B, X page 3-121 0x00000000 Base Address Monitor Vector Base Address R/W, X page 3-122 0x00000000 Interrupt Status page 3-123 0x00000000 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-17 ID012310 Non-Confidential, Unrestricted Access...
Page 150 System Validation Operations 0x00000000 page 3-142 a. See c0, Main ID Register on page 3-20 for the values of bits [23:20] and bits [3:0]. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-18 ID012310 Non-Confidential, Unrestricted Access...
Page 151: Table 3-3 Summary Of Cp15 Mcrr Operations
Invalidate instruction cache range page 3-69 Invalidate data cache range page 3-69 Clean data cache range page 3-69 Clean and invalidate data cache range page 3-69 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-19 ID012310 Non-Confidential, Unrestricted Access...
Page 152: Table 3-4 Main Id Register Bit Functions
Table 3-5 Results of access to the Main ID Register Secure Privileged Non-secure Privileged User Read Write Read Write Data Undefined exception Data Undefined exception Undefined exception ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-20 ID012310 Non-Confidential, Unrestricted Access...
Page 153: Table 3-6 Cache Type Register Bit Functions
Field name Function [31:29] [28:25] Ctype The Cache type and Separate bits provide information about the cache architecture. b1110, indicates that the ARM1176JZF-S processor supports: • write back cache • Format C cache lockdown • Register 7 cache cleaning operations.
Page 154 The P, Page, bit indicates restrictions on page allocation for bits [13:12] of the VA For ARM1176JZF-S processors, the P bit is set if the cache size is greater than 16KB. For more details see Restrictions on page table mappings page coloring on page 6-41.
Page 155: Table 3-7 Results Of Access To The Cache Type Register
CRm set to c0 • Opcode_2 set to 1. For example: MRC p15,0,<Rd>,c0,c0,1; returns cache details Table 3-8, for example, lists the Cache Type Register values for an ARM1176JZF-S processor with: • separate instruction and data caches • cache size = 16KB •...
Page 156: Table 3-9 Tcm Status Register Bit Functions
Data TCMs available in the processor. Table 3-9 lists the purposes of the individual bits in the TCM Status Register. Note In the ARM1176JZF-S processor there is a maximum of two Instruction TCMs and two Data TCMs. The TCM Status Register is: •...
Page 157: Table 3-10 Tlb Type Register Bit Functions
DLsize Data lockable size specifies the number of unified or data TLB lockable entries 0x08 , indicates the ARM1176JZF-S processors has 8 unified TLB lockable entries [7:1] UNP/SBZ Unified specifies if the TLB is unified, 0, or if there are separate instruction and data TLBs, 1.
Page 158: Table 3-12 Processor Feature Register 0 Bit Functions
Figure 3-14 Processor Feature Register 0 format Table 3-12 Processor Feature Register 0 bit functions Bits Field name Function [31:28] Reserved. RAZ. [27:24] Reserved. RAZ. [23:20] Reserved. RAZ. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-26 ID012310 Non-Confidential, Unrestricted Access...
Page 159: Table 3-13 Results Of Access To The Processor Feature Register 0
, ARM1176JZF-S processors support Java. [7:4] State1 Indicates type of Thumb encoding that the processor supports. , ARM1176JZF-S processors support Thumb-1 but do not support Thumb-2. [3:0] State0 Indicates support for 32-bit ARM instruction set. , ARM1176JZF-S processors support 32-bit ARM instructions.
Page 160: Table 3-14 Processor Feature Register 1 Bit Functions
[19:16] Reserved. RAZ. [15:12] Reserved. RAZ. [11:8] Microcontroller programmer’s model Indicates support for the ARM microcontroller programmer’s model. , Not supported by ARM1176JZF-S processors. [7:4] Security extension Indicates support for Security Extensions Architecture v1. , ARM1176JZF-S processors support Security Extensions Architecture v1, TrustZone.
Page 161: Table 3-16 Debug Feature Register 0 Bit Functions
, ARM1176JZF-S processors do not support this debug model. [7:4] Indicates the type of Secure debug model that the processor supports. , ARM1176JZF-S processors support the v6.1 Secure debug architecture based model. [3:0] Indicates the type of applications processor debug model that the processor supports.
Page 162: Table 3-18 Auxiliary Feature Register 0 Bit Functions
[3:0] Implementation Defined. The contents of the Auxiliary Feature Register 0 [31:16] are Reserved. The contents of the Auxiliary Feature Register 0 [15:0] are Implementation Defined. In the ARM1176JZF-S processor, the Auxiliary Feature Register 0 reads as 0x00000000 Table 3-19 lists the results of attempted access for each mode.
Page 163: Table 3-20 Memory Model Feature Register 0 Bit Functions
Indicates support for FCSE. , ARM1176JZF-S processors support FCSE. [23:20] Indicates support for the ARMv6 Auxiliary Control Register. , ARM1176JZF-S processors support the Auxiliary Control Register. [19:16] Indicates support for TCM and associated DMA. , ARM1176JZF-S processors support ARMv6 TCM and DMA.
Page 164: Table 3-22 Memory Model Feature Register 1 Bit Functions
[31:28] Indicates support for branch target buffer. , ARM1176JZF-S processors require flushing of branch predictor on VA change. [27:24] Indicates support for test and clean operations on data cache, Harvard or unified architecture. , no support in ARM1176JZF-S processors.
Page 165: Table 3-23 Results Of Access To The Memory Model Feature Register 1
32-bit read-only register common to the Secure and Non-secure worlds • accessible in privileged modes only. Figure 3-19 on page 3-34 shows the bit arrangement for Memory Model Feature Register 2. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-33 ID012310 Non-Confidential, Unrestricted Access...
Page 166: Table 3-24 Memory Model Feature Register 2 Bit Functions
Indicates support for a Hardware access flag. , no support in ARM1176JZF-S processors. [27:24] Indicates support for Wait For Interrupt stalling. , ARM1176JZF-S processors support Wait For Interrupt. [23:20] Indicates support for memory barrier operations. , ARM1176JZF-S processors support: •...
Page 167: Table 3-25 Results Of Access To The Memory Model Feature Register 2
Support for hierarchical cache maintenance by MVA, all architectures , no support in ARM1176JZF-S processors. [3:0] Support for hierarchical cache maintenance by Set/Way, all architectures. , no support in ARM1176JZF-S processors. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-35 ID012310 Non-Confidential, Unrestricted Access...
Page 168: Table 3-27 Results Of Access To The Memory Model Feature Register 3
Reserved. RAZ. [27:24] Indicates support for divide instructions. , no support in ARM1176JZF-S processors. [23:20] Indicates support for debug instructions. , ARM1176JZF-S processors support BKPT. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-36 ID012310 Non-Confidential, Unrestricted Access...
Page 169: Table 3-29 Results Of Access To The Instruction Set Attributes Register 0
, ARM1176JZF-S processors support CLZ. [3:0] Indicates support for atomic load and store instructions. , ARM1176JZF-S processors support SWP and SWPB. Table 3-29 lists the results of attempted access for each mode. Table 3-29 Results of access to the Instruction Set Attributes Register 0...
Page 170: Table 3-30 Instruction Set Attributes Register 1 Bit Functions
Table 3-30 Instruction Set Attributes Register 1 bit functions Bits Field name Function [31:28] Indicates support for Java instructions. , ARM1176JZF-S processors support BXJ and J bit in PSRs. [27:24] Indicates support for interworking instructions. , ARM1176JZF-S processors support: • BX, and T bit in PSRs •...
Page 171: Table 3-32 Instruction Set Attributes Register 2 Bit Functions
Indicates support for reversal instructions. , ARM1176JZF-S processors support REV, REV16, and REVSH. [27:24] Indicates support for PSR instructions. , ARM1176JZF-S processors support MRS and MSR exception return instructions for data-processing. [23:20] Indicates support for advanced unsigned multiply instructions. , ARM1176JZF-S processors support: •...
Page 172: Table 3-33 Results Of Access To The Instruction Set Attributes Register 2
Field Bits Function name [11:8] Indicates support for multi-access interruptible instructions. , ARM1176JZF-S processors support restartable LDM and STM. [7:4] Indicates support for memory hint instructions. , ARM1176JZF-S processors support PLD. [3:0] Indicates support for load and store instructions. , ARM1176JZF-S processors support LDRD and STRD.
Page 173: Table 3-34 Instruction Set Attributes Register 3 Bit Functions
, ARM1176JZF-S processors support NOP and the capability for additional NOP compatible hints. ARM1176JZF-S processors do not support NOP16. [23:20] Indicates support for Thumb copy instructions. , ARM1176JZF-S processors support Thumb MOV(3) low register ⇒ low register, and the CPY alias for Thumb MOV(3). [19:16] Indicates support for table branch instructions.
Page 174: Table 3-36 Instruction Set Attributes Register 4 Bit Functions
, ARM1176JZF-S processors support all synchronization primitive instructions. See Table 3-34 on page 3-41. [19:16] Indicates support for barrier instructions. , None. ARM1176JZF-S processors support only the CP15 barrier operations. [15:12] Indicates support for SMC instructions. , ARM1176JZF-S processors support SMC.
Page 175: Table 3-37 Results Of Access To The Instruction Set Attributes Register 4
The contents of the Instruction Set Attributes Register 5 are implementation defined. In the ARM1176JZF-S processor, Instruction Set Attributes Register 5 is read as 0x00000000 Table 3-38 lists the results of attempted access for each mode.
Page 176: Figure 3-26 Control Register Format
4 3 2 1 0 U FI SBZ IT V I Z F R S B W C A Figure 3-26 Control Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-44 ID012310 Non-Confidential, Unrestricted Access...
Page 177: Table 3-39 Control Register Bit Functions
1 = Low interrupt latency configuration enabled. See Low interrupt latency configuration on page 2-40. [20:19] UNP/SBZ [18] IT bit Deprecated. Global enable for instruction TCM. Function redundant in ARMv6. [17] UNP/SBZ ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-45 ID012310 Non-Confidential, Unrestricted Access...
Page 178 Function redundant in ARMv6. [15] L4 bit Secure Determines if the T bit is set for PC load instructions. For more details see the ARM modify Architecture Reference Manual. only 0 = Loads to PC set the T bit, reset value.
Page 179: Table 3-40 Results Of Access To The Control Register
Normally, to set the V bit and the B, EE, and U bits you configure signals at reset. The V bit depends on VINITHI at reset: VINITHI LOW sets V to 0 • VINITHI HIGH sets V to 1. • ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-47 ID012310 Non-Confidential, Unrestricted Access...
Page 180: Table 3-41 Resultant B Bit, U Bit, And Ee Bit Values
In ARMv6, the TCM blocks have individual enables that apply to each block. As a result, this bit is now redundant and Should Be One. See c9, Data TCM Region Register on page 3-89 for a description of the ARM1176JZF-S TCM enables. IT bit This bit is used in ARM946 and ARM966 processors to enable the Instruction TCM.
Page 181: Table 3-42 Auxiliary Control Register Bit Functions
1 = Cache size limited to 16KB. Disables block transfer cache operations: 0 = Block transfer cache operations enabled, reset value 1 = Block transfer cache operations disabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-49 ID012310 Non-Confidential, Unrestricted Access...
Page 182: Table 3-43 Results Of Access To The Auxiliary Control Register
MRC p15, 0, <Rd>, c1, c0, 1 ; Read Auxiliary Control Register MCR p15, 0, <Rd>, c1, c0, 1 ; Write Auxiliary Control Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-50 ID012310 Non-Confidential, Unrestricted Access...
Page 183: Table 3-44 Coprocessor Access Control Register Bit Functions
Undefined exception Data Data Data Data Undefined exception To use the Coprocessor Access Control Register read or write CP15 with: • Opcode_1 set to 0 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-51 ID012310 Non-Confidential, Unrestricted Access...
Page 184: Table 3-46 Secure Configuration Register Bit Functions
Function [31:7] UNP/SBZ. The Early Termination bit is not implemented in ARM1176JZF-S processors. UNP/SBZ. Determines if the A bit in the CPSR can be modified when in the Non-secure world: 0 = Disable modification of the A bit in the CPSR in the Non-secure world, reset value 1 = Enable modification of the A bit in the CPSR in the Non-secure world.
Page 185: Table 3-47 Operation Of The Fw And Fiq Bits
NS bit. However, Monitor mode code can access nonsecure banked copies of registers if the NS bit is set to 1. See the ARM Architecture Reference Manual for information on the effect of the Security Extensions on the CP15 registers.
Page 186: Table 3-49 Secure Debug Enable Register Bit Functions
Enables Secure User invasive debug: 0 = Invasive debug is not permitted in Secure User mode, reset value 1 = Invasive debug is permitted in Secure User mode. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-54 ID012310 Non-Confidential, Unrestricted Access...
Page 187: Table 3-50 Results Of Access To The Coprocessor Access Control Register
Non-secure world • only accessible in privileged modes. Figure 3-31 on page 3-56 shows the arrangement of bits in the register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-55 ID012310 Non-Confidential, Unrestricted Access...
Page 188: Table 3-51 Non-Secure Access Control Register Bit Functions
Determines permission to access the given coprocessor in the Non-secure world: 0 = Secure access only, reset value 1 = Secure or Non-secure access. a. n is the coprocessor number from 0 to 13. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-56 ID012310 Non-Confidential, Unrestricted Access...
Page 189: Table 3-52 Results Of Access To The Auxiliary Control Register
Figure 3-32 shows the bit arrangement for the Translation Table Base Register 0. 14-N 13-N Translation table base 0 UNP/SBZ Figure 3-32 Translation Table Base Register 0 format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-57 ID012310 Non-Confidential, Unrestricted Access...
Page 190: Table 3-53 Translation Table Base Register 0 Bit Functions
= Write-back, No Allocate on Write. If the processor supports ECC, it indicates to the memory controller it is enabled or disabled. For ARM1176JZF-S processors this is 0: 0 = Error-Correcting Code (ECC) is disabled, reset value 1 = ECC is enabled.
Page 191: Table 3-55 Translation Table Base Register 1 Bit Functions
; Write Translation Table Base Register 0 Note The ARM1176JZF-S processor cannot page table walk from level one cache. Therefore, if C is set to 1, to ensure coherency, you must either store page tables in Inner write-through memory or, if in Inner write-back, you must clean the appropriate cache entries after modification so that the mechanism for the hardware page table walks sees them.
Page 192: Table 3-56 Results Of Access To The Translation Table Base Register 1
; Write Translation Table Base Register 1 Note The ARM1176JZF-S processor cannot page table walk from level one cache. Therefore, if C is set to 1, to ensure coherency, you must either store page tables in Inner write-through memory or, if in Inner write-back, you must clean the appropriate cache entries after modification so that the mechanism for the hardware page table walks sees them.
Page 193: Table 3-57 Translation Table Base Control Register Bit Functions
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-61 ID012310...
Page 194: Table 3-58 Results Of Access To The Translation Table Base Control Register
Register 0, otherwise use Translation Table Base Register 1. N must be in the range 0-7. Note The ARM1176JZF-S processor cannot page table walk from level one cache. Therefore, if C is set to 1, to ensure coherency, you must either store page tables in Inner write-through memory or, if in Inner write-back, you must clean the appropriate cache entries after modification so that the mechanism for the hardware page table walks sees them.
Page 195: Table 3-59 Domain Access Control Register Bit Functions
To use the Domain Access Control Register read or write CP15 c3 with: • Opcode_1 set to 0 • CRn set to c3 • CRm set to c0 • Opcode_2 set to 0. For example: ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-63 ID012310 Non-Confidential, Unrestricted Access...
Page 196: Table 3-61 Data Fault Status Register Bit Functions
[10] Part of the Status field. See Bits [3:0] in this table. The reset value is 0. [9:8] Always read as 0. Writes ignored. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-64 ID012310 Non-Confidential, Unrestricted Access...
Page 197 = no function b1011 = no function b1100 = no function b1101 = no function b1110 = no function b1111 = no function. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-65 ID012310 Non-Confidential, Unrestricted Access...
Page 198: Table 3-62 Results Of Access To The Data Fault Status Register
Figure 3-37 shows the bit arrangement of the Instruction Fault Status Register. UNP/SBZ UNP/SBZ Status Figure 3-37 Instruction Fault Status Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-66 ID012310 Non-Confidential, Unrestricted Access...
Page 199: Table 3-63 Instruction Fault Status Register Bit Functions
Table 3-64 Results of access to the Instruction Fault Status Register Secure Privileged Non-secure Privileged User Read Write Read Write Secure data Secure data Non-secure data Non-secure data Undefined exception ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-67 ID012310 Non-Confidential, Unrestricted Access...
Page 200: Table 3-65 Results Of Access To The Fault Address Register
A write to this register sets the FAR to the value of the data written. This is useful for a debugger to restore the value of the FAR. The ARM1176JZF-S processor also updates the FAR on debug exception entry because of watchpoints, see Effect of a debug event on CP15 registers on page 13-34 for more details.
Page 201: Table 3-66 Results Of Access To The Instruction Fault Address Register
— virtual to physical address translation. • implement the Data Synchronization Barrier (DSB) operation • implement the Data Memory Barrier (DMB) operation ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-69 ID012310 Non-Confidential, Unrestricted Access...
Page 202: Figure 3-38 Cache Operations
Figure 3-38 Cache operations Figure 3-39 on page 3-71 shows the arrangement of the 4 functions in this group that operate with the MCRR instruction. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-70 ID012310 Non-Confidential, Unrestricted Access...
Page 203: Figure 3-39 Cache Operations With Mcrr Instructions
— MCR p15,0,<Rd>,c7,c15,{0-7} • In the ARM1176JZF-S processor, reading from c7, except for reads from the Cache Dirty Status Register or PA Register, causes an Undefined instruction trap. • Writes to the Cache Dirty Status Register cause an Undefined exception.
Page 204: Table 3-67 Functional Bits Of C7 For Set And Index
The terms used to describe the invalidate, clean, and prefetch operations are as defined in the Caches and Write Buffers chapter of the ARM Architecture Reference Manual. For details of the behavior of c7 in the Secure and Non-secure worlds, see TrustZone behavior on page 3-77.
Page 205: Table 3-69 Functional Bits Of C7 For Mva
Figure 3-42 shows the VA format for invalidate and clean operations. All VA format operations use the MCRR instruction. Virtual address Figure 3-42 Format of c7 for VA ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-73 ID012310 Non-Confidential, Unrestricted Access...
Page 206: Table 3-70 Functional Bits Of C7 For Va Format
Data Cache. These are blocking operations that can be interrupted. If they are interrupted, the R14 value that is ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-74 ID012310...
Page 207: Table 3-72 Cache Operations For Single Lines
Clean Data Cache Line, using MVA MCR p15, 0, <Rd>, c7, c10, 1 Set/Index Clean Data Cache Line, using Index MCR p15, 0, <Rd>, c7, c10, 2 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-75 ID012310 Non-Confidential, Unrestricted Access...
Page 208: Table 3-73 Cache Operations For Address Ranges
FCSE logic. Each of the range operations operates between cache lines containing the and the , inclusive of Start Address End Address Start Address End Address ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-76 ID012310 Non-Confidential, Unrestricted Access...
Page 209: Figure
If the Start Address is greater than the End Address the effect is architecturally Unpredictable. The ARM1176JZF-S processor does not perform cache operations in this case. All block transfers are interruptible. When Block transfers are interrupted, the R14 value that is captured is the address of the instruction that launched the block operation + 4.
Page 210: Table 3-74 Cache Dirty Status Register Bit Functions
CRm set to c10 • Opcode_2 set to 6. For example: MRC p15, 0, <Rd>, c7, c10, 6 ; Read Cache Dirty Status Register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-78 ID012310 Non-Confidential, Unrestricted Access...
Page 211: Table 3-75 Cache Operations Flush Functions
Secure and Non-secure worlds and for address translation between the Secure and Non-secure worlds. VA to PA translations operate through: • PA Register on page 3-80 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-79 ID012310 Non-Confidential, Unrestricted Access...
Page 212: Table 3-77 Pa Register For Successful Translation Bit Functions
0 = Secure memory 1 = Non-secure memory. Not used in the ARM1176JZF-S processor. UNP/SBZ. Indicates shareable memory: 0 = Non-shared 1 = Shared. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-80 ID012310 Non-Confidential, Unrestricted Access...
Page 213: Table 3-78 Pa Register For Unsuccessful Translation Bit Functions
EA bit in the Secure Configuration Register is not set, the processor updates the Secure or Non-secure versions of the two registers, depending on the Secure or Non-secure state of the core when the operation was issued. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-81 ID012310 Non-Confidential, Unrestricted Access...
Page 214 ;User write permission, the PA is loaded ;in PA register, otherwise abort information is ;loaded in PA Register MRC p15,0,<Rd>,c7,c4,0 ;read in <Rd> the PA value ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-82 ID012310 Non-Confidential, Unrestricted Access...
Page 215 Write Barrier in earlier versions of the architecture. The Data Synchronization Barrier operation is: • in CP15 c7 • 32-bit write-only access, common to both Secure and Non-secure worlds ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-83 ID012310 Non-Confidential, Unrestricted Access...
Page 216: Table 3-79 Results Of Access To The Data Synchronization Barrier Operation
For more details, see Explicit Memory Barriers on page 6-25. Note The W bit that usually enables the Write Buffer is not implemented in ARM1176JZF-S processors, see c1, Control Register on page 3-44. This instruction acts as an explicit memory barrier. This instruction completes when all explicit memory transactions occurring in program order before this instruction are completed.
Page 217: Table 3-80 Results Of Access To The Data Memory Barrier Operation
The return link in R14_irq or R14_fiq contains the address of the MCR instruction plus 8, so that the normal instruction used for interrupt return ( SUBS PC,R14,#4 returns to the instruction following the MCR. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-85 ID012310 Non-Confidential, Unrestricted Access...
Page 218: Table 3-82 Results Of Access To The Tlb Operations Register
Data TLB • Unified TLB. Note The ARM1176JZF-S processor has a unified TLB. Any TLB operations specified for the Instruction or Data TLB perform the equivalent operation on the unified TLB. The TLB Operations Register is: • in CP15 c8 •...
Page 219: Figure 3-47 Tlb Operations Register Mva And Asid Format
With these registers you can lock down each cache way independently. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-87 ID012310 Non-Confidential, Unrestricted Access...
Page 220: Table 3-83 Instruction And Data Cache Lockdown Register Bit Functions
Random or Round-Robin cache policy, see c1, Control Register on page 3-44. ARM1176JZF-S processors have an associativity of 4. With all ways locked, the ARM1176JZF-S processor behaves as if only ways 3 to 1 are locked and way 0 is unlocked. ARM DDI 0301H Copyright ©...
Page 221 The purpose of the Data TCM Region Register is to describe the physical base address and size of the Data TCM region and to provide a mechanism to enable it. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-89 ID012310...
Page 222: Table 3-85 Data Tcm Region Register Bit Functions
When the NS access bit is 0 for Data TCM, see c9, Data TCM Non-secure Control Access Register on page 3-93, attempts to access the Data TCM Region Register from the Non-secure world cause an Undefined exception. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-90 ID012310 Non-Confidential, Unrestricted Access...
Page 223: Table 3-86 Results Of Access To The Data Tcm Region Register
Figure 3-51 shows the bit arrangement for the Instruction TCM Region Register. 12 11 2 1 0 Base address (physical address) SBZ/UNP Size Figure 3-51 Instruction TCM Region Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-91 ID012310 Non-Confidential, Unrestricted Access...
Page 224: Table 3-87 Instruction Tcm Region Register Bit Functions
When the NS access bit is 0 for Instruction TCM, see c9, Instruction TCM Non-secure Control Access Register on page 3-94, attempts to access the Instruction TCM Region Register from the Non-secure world cause an Undefined exception. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-92 ID012310 Non-Confidential, Unrestricted Access...
Page 225: Table 3-88 Results Of Access To The Instruction Tcm Region Register
Figure 3-52 shows the bit arrangement for the Data TCM Non-secure Control Access Register. NS access Figure 3-52 Data TCM Non-secure Control Access Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-93 ID012310 Non-Confidential, Unrestricted Access...
Page 226: Table 3-89 Data Tcm Non-Secure Control Access Register Bit Functions
The purpose of the Instruction TCM Non-secure Control Access Register is to: • set access permission to the Instruction TCM Region Register • define instructions in the Instruction TCM as Secure or Non-secure. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-94 ID012310 Non-Confidential, Unrestricted Access...
Page 227: Table 3-91 Instruction Tcm Non-Secure Control Access Register Bit Functions
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-95 ID012310...
Page 228: Table 3-93 Tcm Selection Register Bit Functions
= TCM 1. When there is only one TCM on both Instruction and Data sides, write access is ignored. b10 = Write access ignored. b11 = Write access ignored. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-96 ID012310 Non-Confidential, Unrestricted Access...
Page 229: Table 3-94 Results Of Access To The Tcm Selection Register
Figure 3-55 shows the bit arrangement for the Cache Behavior Override Register. 6 5 4 3 2 1 0 S_WT S_IL S_DL NS_WT NS_IL NS_DL Figure 3-55 Cache Behavior Override Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-97 ID012310 Non-Confidential, Unrestricted Access...
Page 230: Table 3-95 Cache Behavior Override Register Bit Functions
FW bit is clear, see c1, Secure Configuration Register on page 3-52. In this case, the Secure world can read or write the Non-secure locations in the cache, so potentially causing the ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-98 ID012310...
Page 231 The CP14 register has precedence over the CP15 register when the core is in Debug state, and the CP15 register has precedence over the CP14 register in functional states. For more information on cache debug, see Chapter 13 Debug. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-99 ID012310 Non-Confidential, Unrestricted Access...
Page 232: Table 3-97 Tlb Lockdown Register Bit Functions
Data Data Undefined exception The lockdown region of the TLB contains eight entries. TLB organization on page 6-4 describes the structure of the TLB. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-100 ID012310 Non-Confidential, Unrestricted Access...
Page 233 Instruction side, and DMA. Table 3-99 on page 3-102 lists the purposes of the individual bits in the Primary Region Remap Register. Table 3-101 on page 3-103 lists the purposes of the individual bits in the Normal Memory Remap Register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-101 ID012310 Non-Confidential, Unrestricted Access...
Page 234: Table 3-99 Primary Region Remap Register Bit Functions
= reset value [1:0] Remaps {TEX[0],C,B} = b000 b00 = reset value a. The reset values ensure that no remapping occurs at reset ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-102 ID012310 Non-Confidential, Unrestricted Access...
Page 235: Table 3-100 Encoding For The Remapping Of The Primary Memory Type
[17:16] Remaps Outer attribute for {TEX[0],C,B} = b000 b00 = reset value [15:14] Remaps Inner attribute for {TEX[0],C,B} = b111 b01 = reset value ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-103 ID012310 Non-Confidential, Unrestricted Access...
Page 236: Table 3-102 Remap Encoding For Inner Or Outer Cacheable Attributes
To use the memory region remap registers read or write CP15 with: • Opcode_1 set to 0 • CRn set to c10 • CRm set to c2 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-104 ID012310 Non-Confidential, Unrestricted Access...
Page 237 IMB operation before you can rely on the new written values. You must also stop the DMA if it is running or queued. Note You cannot remap the NS bit. This is for security reasons. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-105 ID012310 Non-Confidential, Unrestricted Access...
Page 238: Table 3-104 Dma Identification And Status Register Bit Functions
0 = the channel is not Present 1 = the channel is Present. Indicates channel queued: 0 = the channel is not Queued 1 = the channel is Queued. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-106 ID012310 Non-Confidential, Unrestricted Access...
Page 239: Table 3-106 Results Of Access To The Dma Identification And Status Registers
32-bit read/write register common to the Secure and Non-secure worlds • accessible in privileged modes only. Figure 3-60 on page 3-108 shows the bit arrangement for the DMA User Accessibility Register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-107 ID012310 Non-Confidential, Unrestricted Access...
Page 240: Table 3-107 Dma User Accessibility Register Bit Functions
DMA External Start Address Register on page 3-115 • c11, DMA Internal End Address Register on page 3-116 • c11, DMA Channel Status Register on page 3-117. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-108 ID012310 Non-Confidential, Unrestricted Access...
Page 241: Table 3-109 Dma Channel Number Register Bit Functions
Undefined exception Undefined exception Data Data Undefined exception Undefined exception Either or both 1 Data Undefined exception Data Undefined exception Data Data Data Data ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-109 ID012310 Non-Confidential, Unrestricted Access...
Page 242 The Clear command causes the channel status to change from Complete or Error to Idle. It also clears: • all the Error bits for that DMA channel ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-110 ID012310 Non-Confidential, Unrestricted Access...
Page 243: Table 3-111 Results Of Access To The Dma Enable Registers
To avoid this situation you must ensure the level one DMA issues a Stop command to stop Running or Queued channels when entering debug. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-111 ID012310 Non-Confidential, Unrestricted Access...
Page 244: Table 3-112 Dma Control Register Bit Functions
U bit set to 1 Interrupt on Error regardless of the value written to this bit. [27] Read As One, Write ignored In the ARM1176JZF-S this bit has no effect. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved.
Page 245: Table 3-113 Results Of Access To The Dma Control Register
DMA channel and read or write CP15 with: • Opcode_1 set to 0 • CRn set to c11 • CRm set to c4 • Opcode_2 set to 0. For example: ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-113 ID012310 Non-Confidential, Unrestricted Access...
Page 246: Table 3-114 Results Of Access To The Dma Internal Start Address Register
While the channel has the status of Running or Queued, any attempt to write to the DMA Control Register results in architecturally Unpredictable behavior. For ARM1176JZF-S processors writes to the DMA Control Register have no effect when the DMA channel is running or queued.
Page 247: Table 3-115 Results Of Access To The Dma External Start Address Register
MRC p15, 0, <Rd>, c11, c6, 0 ; Read DMA External Start Address Register MCR p15, 0, <Rd>, c11, c6, 0 ; Write DMA External Start Address Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-115 ID012310 Non-Confidential, Unrestricted Access...
Page 248: Table 3-116 Results Of Access To The Dma Internal End Address Register
MRC p15, 0, <Rd>, c11, c7, 0 ; Read DMA Internal End Address Register MCR p15, 0, <Rd>, c11, c7, 0 ; Write DMA Internal End Address Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-116 ID012310 Non-Confidential, Unrestricted Access...
Page 249: Table 3-117 Dma Channel Status Register Bit Functions
The ISX[0] bit adds a SLVERR or DECERR qualifier to the IS encoding. Only predictable on IS encodings of b11100 and b11110, otherwise UNP/SBZ. For the predictable encodings:0 = DECERR1 = SLVERR. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-117 ID012310 Non-Confidential, Unrestricted Access...
Page 250 The external start and end addresses and the Stride must all be multiples of the transaction size. If this is not the case, the BP bit is set to 1, and the DMA channel does not start. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-118 ID012310...
Page 251: Table 3-118 Results Of Access To The Dma Channel Status Register
In the event of an external abort on a page table walk caused by the DMA, the processor asserts the nDMAEXTERRIRQ output. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-119 ID012310 Non-Confidential, Unrestricted Access...
Page 252: Table 3-119 Dma Context Id Register Bit Functions
MRC p15, 0, <Rd>, c11, c15, 0 ; Read DMA Context ID Register MCR p15, 0, <Rd>, c11, c15, 0 ; Write DMA Context ID Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-120 ID012310 Non-Confidential, Unrestricted Access...
Page 253: Table 3-121 Secure Or Non-Secure Vector Base Address Register Bit Functions
When an exception occurs in the Non-secure world, the core branches to address: Non-secure Vector_Base_Address + Exception_Vector_Address. When high vectors are enabled, regardless of the value of the register the core branches to: + Exception_Vector_Address 0xFFFF0000 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-121 ID012310 Non-Confidential, Unrestricted Access...
Page 254: Table 3-122 Results Of Access To The Secure Or Non-Secure Vector Base Address Register
Secure privileged modes only. Figure 3-66 shows the arrangement of bits in the register. Monitor vector base address Figure 3-66 Monitor Vector Base Address Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-122 ID012310 Non-Confidential, Unrestricted Access...
Page 255: Table 3-123 Monitor Vector Base Address Register Bit Functions
The purpose of the Interrupt Status Register is to: reflect the state of the nFIQ and nIRQ pins on the processor • • to reflect the state of external aborts. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-123 ID012310 Non-Confidential, Unrestricted Access...
Page 256: Table 3-125 Interrupt Status Register Bit Functions
The A, I, and F bits map to the same format as the CPSR so that you can use the same mask for these bits. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-124 ID012310 Non-Confidential, Unrestricted Access...
Page 257 • CRm set to c1 • Opcode_2 set to 0. For example: MRC p15, 0, <Rd>, c12, c1, 0 ; Read Interrupt Status Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-125 ID012310 Non-Confidential, Unrestricted Access...
Page 258: Table 3-127 Fcse Pid Register Bit Functions
MRC p15, 0, <Rd>, c13, c0, 0 ; Read FCSE PID Register MCR p15, 0, <Rd>, c13, c0, 0 ; Write FCSE PID Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-126 ID012310 Non-Confidential, Unrestricted Access...
Page 259: Figure 3-69 Address Mapping With The Fcse Pid Register
128 x 32MB processes to be mapped. Note If ProcID is 0, as it is on Reset, then there is a flat mapping between the ARM1176JZF-S processor and the MMU. Figure 3-69 shows how addresses are mapped using the FCSE PID Register.
Page 260: Table 3-129 Context Id Register Bit Functions
CRn set to c13 • CRm set to c0 • Opcode_2 set to 1. For example: MRC p15, 0, <Rd>, c13, c0, 1 ;Read Context ID Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-128 ID012310 Non-Confidential, Unrestricted Access...
Page 261: Table 3-131 Results Of Access To The Thread And Process Id Registers
To use the thread and process ID registers read or write CP15 with: • Opcode_1 set to 0 • CRn set to c13 • CRm set to c0 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-129 ID012310 Non-Confidential, Unrestricted Access...
Page 262: Figure 3-71 Peripheral Port Memory Remap Register Format
Figure 3-71 shows the arrangement of the bits in the register. 12 11 Base address UNP/SBZ Size Figure 3-71 Peripheral Port Memory Remap Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-130 ID012310 Non-Confidential, Unrestricted Access...
Page 263: Table 3-132 Peripheral Port Memory Remap Register Bit Functions
Table 3-133 Results of access to the Peripheral Port Remap Register Secure Privileged Non-secure Privileged User Read Write Read Write Secure data Secure data Non-secure data Non-secure data Undefined exception ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-131 ID012310 Non-Confidential, Unrestricted Access...
Page 264: Table 3-134 Secure User And Non-Secure Access Validation Control Register Bit Functions
Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-132 ID012310...
Page 265: Figure 3-73 Performance Monitor Control Register Format
Figure 3-73 shows the bit arrangement for the Performance Monitor Control Register. 28 27 20 19 12 11 4 3 2 1 0 SBZ/UNP EvtCount0 EvtCount1 Figure 3-73 Performance Monitor Control Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-133 ID012310 Non-Confidential, Unrestricted Access...
Page 266: Table 3-136 Performance Monitor Control Register Bit Functions
1 = Enable interrupt. Cycle count divider: 0 = Counts every processor clock cycle, reset value 1 = Counts every 64th processor clock cycle. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-134 ID012310 Non-Confidential, Unrestricted Access...
Page 267: Table 3-137 Performance Monitoring Events
ETMEXTOUT[0] signal was asserted for a cycle. 0x20 [19] Write Buffer drained because of a Data Synchronization Barrier operation or 0x12 Strongly Ordered operation. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-135 ID012310 Non-Confidential, Unrestricted Access...
Page 269: Table 3-138 Results Of Access To The Performance Monitor Control Register
You can use this register in conjunction with the Performance Monitor Control Register and the two Counter Registers to provide a variety of useful metrics that enable you to optimize system performance. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-137 ID012310 Non-Confidential, Unrestricted Access...
Page 270: Table 3-139 Results Of Access To The Cycle Counter Register
When the core is in a mode where noninvasive debug is not permitted, set by SPNIDEN • and the SUNIDEN bit, see c1, Secure Debug Enable Register on page 3-54, the processor does not count events. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-138 ID012310 Non-Confidential, Unrestricted Access...
Page 271: Table 3-140 Results Of Access To The Count Register 0
When the core is in a mode where non-invasive debug is not permitted, set by SPNIDEN • and the SUNIDEN bit, see c1, Secure Debug Enable Register on page 3-54, the processor does not count events. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-139 ID012310 Non-Confidential, Unrestricted Access...
Page 272: Table 3-141 Results Of Access To The Count Register 1
The reset, interrupt, and fast interrupt counters are 32-bits wide. The external debug request counter is 6 bits wide. Figure 3-74 on page 3-141 shows the arrangement of bits for the external debug request counter. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-140 ID012310 Non-Confidential, Unrestricted Access...
Page 273: Table 3-143 Results Of Access To The System Validation Counter Register
When the counters wrap around they cause the specified event to occur. See c15, System Validation Operations Register on page 3-142. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-141 ID012310 Non-Confidential, Unrestricted Access...
Page 274: Table 3-144 System Validation Operations Register Functions
Opcode_2 that Table 3-144 does not list has no effect. A read from the System Validation Operations Register returns 0x00000000 The reset value of this register is 0. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-142 ID012310 Non-Confidential, Unrestricted Access...
Page 275: Table 3-145 Results Of Access To The System Validation Operations Register
MCR p15, 2, <Rd>, c15, c13, 7 ; Stop reset, interrupt and fast interrupt counters MCR p15, 3, <Rd>, c15, c13, 0 ; Stop external debug request counter ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-143 ID012310 Non-Confidential, Unrestricted Access...
Page 276 Use the Performance Monitor Control Register to reset the counters and return them to System performance monitoring functionality. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-144 ID012310 Non-Confidential, Unrestricted Access...
Page 277: Table 3-146 System Validation Cache Size Mask Register Bit Functions
= 2 banks, 4KB each b101 = 2 banks, 8KB each b110 = 2 banks, 16KB each b111 = 2 banks, 32KB each. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-145 ID012310 Non-Confidential, Unrestricted Access...
Page 278: Table 3-147 Results Of Access To The System Validation Cache Size Mask Register
MRC p15, 0, <Rd>, c15, c14, 0 ; Read System Validation Cache Size Mask Register MCR p15, 0, <Rd>, c15, c14, 0 ; Write System Validation Cache Size Mask Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-146 ID012310 Non-Confidential, Unrestricted Access...
Page 279 Attempts to write to this register in Secure Privileged mode when CP15SDISABLE is HIGH result in an Undefined exception, see TrustZone write access disable on page 2-9. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-147 ID012310...
Page 280 The <Register Number> field of the instruction designates one of the registers required to capture all the Valid bits. The highest Register Number is one less than the number of times 8KB divides into the cache size. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-148 ID012310 Non-Confidential, Unrestricted Access...
Page 281: Table 3-148 Tlb Lockdown Index Register Bit Functions
Figure 3-77 shows the arrangement of bits in the TLB Lockdown VA Register. 12 11 10 9 8 7 SBZ G ASID Figure 3-77 TLB Lockdown VA Register format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-149 ID012310 Non-Confidential, Unrestricted Access...
Page 282: Table 3-149 Tlb Lockdown Va Register Bit Functions
Defines the size of the memory region that this page table entry describes: b00 = 16MB supersection b01 = 4KB page b10 = 64KB page b11 = 1M section. [5:4] UNP/SBZ. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-150 ID012310 Non-Confidential, Unrestricted Access...
Page 283: Table 3-151 Access Permissions Apx And Ap Bit Fields Encoding
Should Be Zero. [27:26] Sub-page access permissions for the second sub-page. If the page table entry does not support sub-pages this field Should Be Zero. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-151 ID012310 Non-Confidential, Unrestricted Access...
Page 284: Table 3-153 Results Of Access To The Tlb Lockdown Access Registers
TLB lockdown access registers. Note Software must avoid the creation of inconsistencies between the main TLB entries and the entries already loaded in the micro-TLBs. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-152 ID012310 Non-Confidential, Unrestricted Access...
Page 285 ; Write TLB Lockdown PA R0,R0,#1 ; Increment counter R0,#8 ; Restored all 8 entries? TLBLockLoad ; Loop until all restored CPSIE ; Re-enable interrupts ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 3-153 ID012310 Non-Confidential, Unrestricted Access...
Page 286 Mixed-endian access support on page 4-17 • Instructions to reverse bytes in a general-purpose register on page 4-20 • Instructions to change the CPSR E bit on page 4-21. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 287: Chapter 4 Unaligned And Mixed-Endian Data Access Support
A byte-invariant addressing scheme to support fine-grain big-endian and little-endian shared data structures, to conform to a shared memory standard. The original ARM architecture was designed as little-endian. This provides a consistent address ordering of bits, bytes, words, cache lines, and pages, and is assumed by the documentation of instruction set encoding and memory and register bit significance.
Page 288: Unaligned Access Support
4.2.1 Legacy support For ARM architectures prior to ARM architecture v6, data access to non-aligned word and halfword data was treated as aligned from the memory interface perspective. That is, the address is treated as truncated with Address[1:0], treated as zero for word accesses, and Address[0] treated as zero for halfword accesses.
Page 289: Table 4-1 Unaligned Access Handling
Word access Memory interface uses Address [31:2]. Address [1:0] asserted as 0. — ARM load data rotates the aligned read data and rotates this right by the byte-offset denoted by Address [1:0], see the ARM Architecture Reference Manual. — ARM and Thumb load-multiple accesses always treated as aligned. No rotation of read data.
Page 290 Subpage AP bits are disabled, that is CP15 c1 bit 23, XP bit, is 1. Swap and synchronization primitives, multiple-word or coprocessor access produce an alignment fault regardless of the setting of the A bit. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 291: Endian Support
Store byte, endian independent The low eight bits of the general-purpose register are stored into the addressed byte in memory, as Figure 4-3 on page 4-7 shows. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 292: Figure 4-3 Store Byte
The addressed byte-pair is loaded from memory into the low 16 bits of the general-purpose register, and the upper 16 bits are zeroed so that the most-significant addressed byte in memory appears in bits [15:8] of the ARM register, as Figure 4-5 on page 4-8 shows. ARM DDI 0301H Copyright ©...
Page 293: Figure 4-5 Load Unsigned Halfword, Big-Endian
The addressed byte-pair is loaded from memory into the low 16-bits of the general-purpose register, so that the most significant addressed byte in memory appears in bits [15:8] of the ARM register and bits [31:16] replicate the sign bit in bit 15, as Figure 4-7 on page 4-9 shows.
Page 294: Figure 4-7 Load Signed Halfword, Big-Endian
The low 16 bits of the general-purpose register are stored into the memory with bits [15:8] written to the addressed byte in memory, bits [7:0] to the incremental byte address in memory, as Figure 4-9 on page 4-10 shows. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 295: Figure 4-9 Store Halfword, Big-Endian
Load word, big-endian The addressed byte-quad is loaded from memory into the 32-bit general-purpose register so that the most significant addressed byte in memory appears in bits [31:24] of the ARM register, as Figure 4-11 on page 4-11 shows. ARM DDI 0301H Copyright ©...
Page 296: Figure 4-11 Load Word, Big-Endian
Abort is generated and the MMU returns a Misaligned fault in the Fault Status Register. 4.3.12 Store word, little-endian The 32-bit general-purpose register is stored to four bytes in memory where bits [7:0] of the ARM register are transferred to the least-significant addressed byte in memory, as Figure 4-12 shows. Register Memory...
Page 297: Figure 4-13 Store Word, Big-Endian
If strict alignment fault checking is enabled and effective Address bits[1:0] are not zero, then a Data Abort is generated and the MMU returns an Alignment fault in the Fault Status Register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-12 ID012310 Non-Confidential, Unrestricted Access...
Page 298: Operation Of Unaligned Accesses
X+3 in the current endianness model, combined to form a word in little-endian order in the LE endianness model or in big-endian order in the BE-8 or BE-32 endianness model. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-13 ID012310 Non-Confidential, Unrestricted Access...
Page 299: Table 4-3 Unalignment Fault Occurrence When Access Behavior Is Architecturally Unpredictable
DWSync Normal Word[Addr] bxx1, DWSync Unpredictable DWord[Align64(Addr)]; Operation unaffected by bx1x, Addr[2:0] b1xx ARMv6 unaligned support bxxx Byte, BSync Normal Byte[Addr] ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-14 ID012310 Non-Confidential, Unrestricted Access...
Page 300 An LDR instruction that loads the PC, has Addr[1:0] != b00, and is specified in the table as having Normal behavior instead has Unpredictable behavior. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-15 ID012310 Non-Confidential, Unrestricted Access...
Page 301 Unpredictable regardless of alignment if the PC is specified as their destination register. The exceptions are ARM LDM and RFE instructions, and Thumbs POP instruction. If the instruction for them is Addr[1:0] != b00, the effective address of the transfer has its two least significant bits forced to 0 if A is set 0 and U is set to 0.
Page 302: Mixed-Endian Access Support
ARMv6 support for mixed-endian data • Instructions to change the CPSR E bit on page 4-21. For more information, see The ARM Architecture Reference Manual. 4.5.1 Legacy fixed instruction and data endianness Prior to ARMv6 the endianness of both instructions and data are locked together, and the configuration of the processor and the external memory system must either be hard-wired or programmed in the first few instructions of the bootstrap code.
Page 303 4-10, BE-8 describes • word store as Store word, little-endian on page 4-11, LE, and Store word, big-endian on page 4-11, BE-8 describes. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-18 ID012310 Non-Confidential, Unrestricted Access...
Page 304: Table 4-5 Mixed-Endian Configuration
Secure and Non-secure reset values of the U and EE bits. Table 4-6 B bit, U bit, and EE bit settings BIGENDINIT UBITINIT ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 4-19 ID012310 Non-Confidential, Unrestricted Access...
Page 305: Instructions To Reverse Bytes In A General-Purpose Register
• Reverse packed halfwords in a register for transforming big- and little-endian 16-bit representations. ARM1176JZF-S instruction set summary on page 1-32 describes these instructions. 4.6.1 All load and store operations All load and store instructions take account of the CPSR E bit. Data is transferred directly to registers when E = 0, and byte reversed if E = 1 for halfword, word, or multiple word transfers.
Page 306: Instructions To Change The Cpsr E Bit
Unaligned and Mixed-endian Data Access Support Instructions to change the CPSR E bit ARM and Thumb instructions are provided to set and clear the E-bit efficiently: Sets the CPSR E bit SETEND BE SETEND LE Resets the CPSR E bit.
Page 307: Chapter 5 Program Flow Prediction
• Branch prediction on page 5-4 • Return stack on page 5-7 • Memory Barriers on page 5-8 • ARM1176JZF-S IMB implementation on page 5-10. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 308: About Program Flow Prediction
For details of CP15 instructions see c7, Cache operations on page 3-69 and Flush operations on page 3-79. The BTAC is globally flushed for: • Main TLB FCSE PID changes ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 309 The PU prefetches all instruction types regardless of the state of the integer core. That is, it performs prefetches in ARM state, Thumb state, and Jazelle state. However the rate at which the PU is drained is state-dependent, and the functioning of the branch prediction hardware is a function of the state.
Page 310: Branch Prediction
Branch prediction In ARM processors that have no PU, the target of a branch is not known until the end of the Execute stage. At the Execute stage it is known whether or not the branch is taken. The best performance is obtained by predicting all branches as not taken and filling the pipeline with the instructions that follow the branch in the current sequential path.
Page 311 The SBP looks at the MSB of the branch offset to determine the branch direction. Statically predicted taken branches incur a one-cycle delay before the target instructions start refilling the pipeline. The SBP works in both ARM and Thumb states. The SBP does not function in Jazelle state.
Page 312 If the prediction was incorrect, the integer core flushes the PU and requests that prefetching begins from the stored recovery address. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 313: Return Stack
Two classes of return stack mispredictions can exist: • condition code failures of the return operation • incorrect return location. In addition, an empty return stack gives no prediction. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 314: Memory Barriers
The ARMv6 architecture mandates three explicit barrier instructions in the System Control Coprocessor to support the memory order model, see the ARM Architecture Reference Manual, and requires these instructions to be available in both Privileged and User modes: •...
Page 315 IMB_Range(unsigned long start_addr, unsigned long end_addr); Where the address range runs from start_addr (inclusive) end_addr (exclusive) . When the standard ARM Procedure Call Standard is used, this means that is passed in R0 and start_addr in R1. end_addr The execution time cost of an IMB can be very large, many thousands of clock cycles, even when a small address range is specified.
Page 316: Arm1176Jzf-S Imb Implementation
ARM1176JZF-S processors. Future processors might implement the IMBRange instruction in a more efficient and faster manner, and code migrated from the ARM1176JZF-S core is likely to benefit when executed on these processors. • ARM1176JZF-S processors implement a Flush Prefetch Buffer operation that is user-accessible and acts as an IMB.
Page 317 Example 5-3 shows this. Example 5-3 Self-decompressing code 0xF00000 ; copy and decompress bulk of code ; start of decompressed code ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 5-11 ID012310 Non-Confidential, Unrestricted Access...
Page 318 Fault status and address on page 6-34 • Hardware page table translation on page 6-36 • MMU descriptors on page 6-43 • MMU software-accessible registers on page 6-53. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 319: Chapter 6 Memory Management Unit
Only global mappings and those for the current application space are enabled at any time. By changing the Application Space IDentifier (ASID) you can alter the enabled set of virtual to physical address mappings. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 320 This attribute is a TrustZone security extension to the existing ARMv6 MMU. It defines when the target memory is Secure or Non-secure. See NS attribute on page 6-19 for a detailed explanation of this bit. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 321: Tlb Organization
The virtual addresses held in the MicroTLB include the FCSE translation from Virtual Address (VA) to Modified Virtual Address (MVA). For more information see the ARM Architecture Reference Manual. The process of loading the MicroTLB from the main TLB includes the FCSE translation if appropriate.
Page 322 Main TLB misses Main TLB misses are handled in hardware by the two level page table walk mechanism, as used on previous ARM processors. See c8, TLB Operations Register on page 3-86. Note Automatic page table walks might be disabled by PD0 and PD1 bits in the TTB Control register.
Page 323: Figure
Figure 6-6 on page 6-38 and Figure 6-9 on page 6-41 show the page table formats of supersections. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 324: Memory Access Sequence
Consist of 16MB blocks of memory. Sections Consist of 1MB blocks of memory. Large pages Consist of 64KB blocks of memory. Small pages Consist of 4KB blocks of memory. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 325 Tightly-Coupled Memory There are no page table restrictions for mappings to the Tightly-Coupled Memory (TCM). For details of the TCM see Tightly-coupled memory on page 7-7. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 326: Enabling And Disabling The Mmu
— those parameters depend on the programming of the PRRR and NMRR registers, see TexRemap=1 configuration on page 6-16 for more information on this behavior. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 327 All CP15 MMU and cache operations can be executed even when the MMU is disabled. • Accesses to the TCMs work as normal if the TCMs are enabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-10 ID012310 Non-Confidential, Unrestricted Access...
Page 328: Memory Access Control
6.5.1 Domains A domain is a collection of memory regions. In compliance with the ARM Architecture and the TrustZone Security Extensions, the ARM1176JZF-S supports 16 Domains in the Secure world and 16 Domains in the Non-secure world. Domains provide support for multi-user operating systems.
Page 329: Table 6-1 Access Permission Bit Encoding
If the XN bit is cleared, then code can execute from that memory region. When the MMU is in ARMv5 mode, see the XP bit in c1, Control Register on page 3-44, the ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-12 ID012310...
Page 330: Figure
XN bit, and all pages are executable. In ARMv6 mode, XP bit =1, the descriptors specify the XN attribute, see Figure 6-7 on page 6-39 and Figure 6-8 on page 6-40. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-13 ID012310 Non-Confidential, Unrestricted Access...
Page 331: Memory Region Attributes
This is the standard ARMv6 configuration. The five TEX[2:0], C, and B bits are used to encode the memory region type. For page tables formats with no TEX field, you must use the value 3'b000. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-14 ID012310 Non-Confidential, Unrestricted Access...
Page 332: Table 6-2 Tex Field, And C And B Bit Encodings Used In Page Table Formats
The C and B bits are described as the AA bits and define the Inner cache policy • The TEX[1:0] bits are described as the BB bits and define the Outer cache policy. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-15 ID012310 Non-Confidential, Unrestricted Access...
Page 333: Table 6-3 Cache Policy Bits
In this configuration the processor provides the OS with a remap capability for the memory attribute. Two CP15 registers, the Primary Region Remap Register (PRRR) and the Normal Memory Region Register (NMRR) come into effect. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-16 ID012310 Non-Confidential, Unrestricted Access...
Page 334: Table 6-5 Effect Of Remapping Memory With Tex Remap = 1
PRRR[1:0] NMRR[1:0] NMRR[17:16] PRRR[3:2] NMRR[3:2] NMRR[19:18] PRRR[5:4] NMRR[5:4] NMRR[21:20] PRRR[7:6] NMRR[7:6] NMRR[23:22] PRRR[9:8] NMRR[9:8] NMRR[25:24] PRRR[11:10] NMRR[11:10] NMRR[27:26] PRRR[13:12] NMRR[13:12] NMRR[29:28[ PRRR[15:14] NMRR[15:14] NMRR[31:30] ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-17 ID012310 Non-Confidential, Unrestricted Access...
Page 335: Table 6-6 Values That Remap The Shareable Attribute
Strongly Ordered regions are remapped as Strongly Ordered and so on. • For security reasons, the NS Attribute bit has no remap capability. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-18 ID012310 Non-Confidential, Unrestricted Access...
Page 336: Figure
There is no check of the NS Attribute internally, and therefore the system can not generate an error because of a wrong NS Attribute. Only external aborts can be generated, if the system has implemented this feature. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-19 ID012310 Non-Confidential, Unrestricted Access...
Page 337: Memory Attributes And Types
For read-only normal memory: • two loads from a specific location return the same data for each load. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-20 ID012310 Non-Confidential, Unrestricted Access...
Page 338 Cacheable attributes, for example by the use of synonyms in a virtual to physical address mapping, results in Unpredictable behavior but does not break security. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-21 ID012310 Non-Confidential, Unrestricted Access...
Page 339 For shared device memory, the data of a write is visible to all observers before the end of a Data Synchronization ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-22 ID012310...
Page 340: Figure
CSPR. This requirement exists only for backwards compatibility with previous versions of the ARM architecture, and the behavior is deprecated in ARMv6. Programs must not rely on this behavior, but instead include an explicit Memory Barrier between the memory access and the following instruction.
Page 341: Figure 6-1 Memory Ordering Restrictions
A2 in program order. • A2 < A1 if the instruction that generates A2 occurs before the instruction that generates A1 in program order. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-24 ID012310 Non-Confidential, Unrestricted Access...
Page 342 These operations are implemented by writing to the CP15 Cache operation register c7. For details on how to use this register see c7, Cache operations on page 3-69. For more information on explicit memory barriers, see the ARM Architecture Reference Manual. Data Memory Barrier This memory barrier ensures that all explicit memory transactions occurring in program order before this instruction are completed.
Page 343: Table 6-10 Memory Region Backwards Compatibility
NCNB, Noncacheable, Non Strongly Ordered Bufferable NCB, Noncacheable, Bufferable Shared Device Write-Through, Cacheable, Non-Shared Normal, Write-Through Bufferable Cacheable Write-Back, Cacheable, Bufferable Non-Shared Normal, Write-Back Cacheable ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-26 ID012310 Non-Confidential, Unrestricted Access...
Page 344: Mmu Aborts
Data Abort, has taken place. The IFAR is updated with the address of the instruction that causes the abort. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-27 ID012310 Non-Confidential, Unrestricted Access...
Page 345 IFAR is updated on an external abort on a hardware page table walk on an instruction access. The appropriate Fault Status Register indicates that this has occurred. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-28 ID012310 Non-Confidential, Unrestricted Access...
Page 346: Mmu Fault Checking
MMU does not retain status about faults generated by instruction fetches. An access violation for a given memory access inhibits any corresponding external access, and an abort is returned to the processor. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-29 ID012310 Non-Confidential, Unrestricted Access...
Page 347: Translation Table Managed Tlb Fault Checking Sequence Part 1
(first level) Section/Page Descriptor translation fault? abort Section/Page Access access flag bit fault? fault Figure 6-2 Translation table managed TLB fault checking sequence part 1 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-30 ID012310 Non-Confidential, Unrestricted Access...
Page 348: Translation Table Managed Tlb Fault Checking Sequence Part 2
Check access permissions Check access permissions Section Sub-page permission permission fault fault Physical address Figure 6-3 Translation table managed TLB fault checking sequence part 2 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-31 ID012310 Non-Confidential, Unrestricted Access...
Page 349 Access Bit records recent TLB access to a page, or section, and the OS can use this to optimize memory managements algorithms. In the ARM1176JZF-S processor the Access Bit must be managed by the software. Reading a page table entry into the TLB when the Access Bit is 0 causes an Access Bit fault.
Page 350 If a watchpoint is taken the WFAR is set to the address that caused the watchpoint. Watchpoints are not taken precisely because following instructions can run underneath load and store multiples. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-33 ID012310 Non-Confidential, Unrestricted Access...
Page 351: Fault Status And Address
Table 6-12 on page 6-35 lists a summary of the abort vector that is taken, and the Fault Status and Fault Address Registers that are updated for each abort type. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-34 ID012310...
Page 352: Table 6-12 Summary Of Aborts
When the EA bit is set, the updated FSR or FAR is always Secure. b. Data Aborts can be precise, see External aborts on page 6-27 for more details. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-35 ID012310...
Page 353: Hardware Page Table Translation
Software can use bits [31:2] for its own purposes in such a descriptor, because they are ignored by the hardware. Where appropriate, ARM Limited recommends that bits [31:2] continue to hold valid access permissions for the descriptor.
Page 354: Figure 6-4 Backwards-Compatible First-Level Descriptor Format
Figure 6-4 Backwards-compatible first-level descriptor format If the P bit is supported and set for the memory region, it indicates to the system memory controller that this memory region has ECC enabled. ARM1176JZF-S processors do not support the P bit.
Page 355: Figure 6-5 Backwards-Compatible Second-Level Descriptor Format
16 consecutive page table locations • the first description must occur on a 16-word boundary For more information see the ARM Architecture Reference Manual. Figure 6-6 shows an overview of the section, supersection, and page translation process using backwards-compatible descriptors.
Page 356: Figure 6-7 Armv6 First-Level Descriptor Formats With Subpages Disabled
If the P bit is supported and set for the memory region, it indicates to the system memory controller that this memory region has ECC enabled. ARM1176JZF-S processors do not support the P bit. In addition to the invalid translation, bits [1:0] = b00, translations for the reserved entry, bits [1:0] = b11, result in a translation fault.
Page 357: Figure 6-8 Armv6 Second-Level Descriptor Format
Bit [0] of the entry is the XN bit for the entry. Figure 6-9 on page 6-41 shows an overview of the section, supersection, and page translation process using ARMv6 descriptors. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-40 ID012310 Non-Confidential, Unrestricted Access...
Page 358: Figure 6-9 Armv6 Section, Supersection, And Page Translation
The same physical address can be mapped by TLB entries of different page sizes, including page sizes over 4KB. Imposing this requirement on the virtual address is called page coloring. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-41 ID012310 Non-Confidential, Unrestricted Access...
Page 359 CP15 Cache Type Register. However, when the CZ flag is set, all caches are limited to 16KB, even if a larger cache size is specified in the CP15 Cache Type Register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-42 ID012310...
Page 360: Mmu Descriptors
8KB, 2048 entries 4KB, 1024 entries 512MB 2KB, 512 entries 256MB 1KB, 256 entries 128MB 512B, 128 entries 64MB 256B, 64 entries 32MB 128B, 32 entries ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-43 ID012310 Non-Confidential, Unrestricted Access...
Page 361: Figure 6-10 Creating A First-Level Descriptor Address
{TTBR0[31:14-N], MVA[31-N:20], 00} Where N is the value of the Translation First-level descriptor address Table Base Control Register c2 Figure 6-10 Creating a first-level descriptor address ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-44 ID012310 Non-Confidential, Unrestricted Access...
Page 362: Table 6-14 Access Types From First-Level Descriptor Bit Values
If bits [1:0] of the first-level descriptor are b10, a request to a section memory block has occurred. Figure 6-11 on page 6-46 shows the translation process for a 1MB section using ARMv6 format, AP bits disabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-45 ID012310 Non-Confidential, Unrestricted Access...
Page 363: Translation For A 1Mb Section, Armv6 Format
AP P Domain 0 C B 1 Physical address 20 19 Section base address Section index Figure 6-12 Translation for a 1MB section, backwards-compatible format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-46 ID012310 Non-Confidential, Unrestricted Access...
Page 364: Table 6-15 Access Types From Second-Level Descriptor Bit Values
Prefetch Abort for the instruction side or a Data Abort for the data side, see MMU fault checking on page 6-29. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-47 ID012310...
Page 365: Figure 6-14 Large Page Table Walk, Armv6 Format
Figure 6-15 on page 6-49 shows the translation process for a 64KB large page, or a 16KB large page subpage, using backwards-compatible format, AP bits enabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-48 ID012310 Non-Confidential, Unrestricted Access...
Page 366: Figure 6-15 Large Page Table Walk, Backwards-Compatible Format
Figure 6-16 on page 6-50 shows the translation process for a 4KB small page or a 1KB small page subpage using backwards-compatible format descriptors, AP bits enabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-49 ID012310...
Page 367: Figure 6-16 4Kb Small Page Or 1Kb Small Subpage Translations, Backwards-Compatible Format
Figure 6-17 on page 6-51 shows the translation process for a 4KB extended small page using ARMv6 format descriptors, AP bits disabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-50 ID012310 Non-Confidential, Unrestricted Access...
Page 368: Figure 6-17 4Kb Extended Small Page Translations, Armv6 Format
Figure 6-18 on page 6-52 shows the translation process for a 4KB extended small page or a 1KB extended small page subpage using backwards-compatible format descriptors, AP bits enabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-51 ID012310...
Page 369: Figure 6-18 4Kb Extended Small Page Or 1Kb Extended Small Subpage Translations
4KB extended small page is converted into four 1KB extended small page subpages. The subpage access permission bits are chosen using the virtual address bits [11:10]. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-52 ID012310...
Page 370: Mmu Software-Accessible Registers
MCR instructions. Registers c5 and c6 are also written by the MMU. Reading CP15 c8 results in an Undefined exception. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-53 ID012310 Non-Confidential, Unrestricted Access...
Page 371: Table 6-17 Cp14 Register Functions
CP14 c11, Debug State MMU Control Register on page 13-23 Debug State Cache Control Register CP14 c10, Debug State Cache Control Register on page 13-23 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 6-54 ID012310 Non-Confidential, Unrestricted Access...
Page 372 • Tightly-coupled memory on page 7-7 • DMA on page 7-10 • TCM and cache interactions on page 7-12 • Write buffer on page 7-16. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 373: Chapter 7 Level One Memory System
The processor caches memory translations in MicroTLBs for each of the instruction and data sides and for the DMA, with a single main TLB backing the MicroTLBs. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 374: Cache Organization
Chapter 3 System Control Coprocessor describes this. Figure 7-1 on page 7-4 shows the block diagram of the cache subsystem. It does not show the cache refill paths. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 375: Figure 7-1 Level One Cache Block Diagram
MicroTLB provides, indicates when the cache line comes from Secure or Non-secure memory. • Cache lines can be either Write-Back or Write-Through, determined by the MicroTLB entry. • Only read allocation is supported. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 376 Cache operations on page 3-69 describes the cache control operations that are supported by the processor. The processor supports all the block cache control operations in hardware. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 377 Cache miss handling when all ways are locked down The ARM architecture describes the behavior of the cache as being Unpredictable when all ways in the cache are locked down. However, for ARM1176JZF-S processors a cache miss is serviced as if Way 0 is not locked.
Page 378: Tightly-Coupled Memory
TCM region and TCM Access Control registers, the TCM Selection registers are set to the TCM of interest, see c9, TCM Selection Register on page 3-96. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 379: Table 7-2 Access To Non-Secure Tcm
CP15 register c9. The disabling of a TCM invalidates the base address, so there is no unexpected hit behavior for the TCM. The timing of a TCM access is the same as for a cache access. The ARM1176JZF-S processor does not support wait states on the TCM interfaces.
Page 380 If the page table entry covers a region larger than the size of the TCM, then the attributes are ignored for the TCM region but still apply to the rest of the region covered by the page table entry. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 381: Dma
DMA to work to either the instruction or data RAMs • DMA is allocated by a privileged process, enabling User access to control the DMA. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-10 ID012310 Non-Confidential, Unrestricted Access...
Page 382 TLB is flushed, while a DMA channel is in the Running or Queued state, then the DMA channel must be stopped. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-11 ID012310 Non-Confidential, Unrestricted Access...
Page 383: Tcm And Cache Interactions
RAMs are different sizes, the regions in physical memory of the two RAMs must not be overlapped. This is because the resulting behavior is architecturally Unpredictable. In these cases, you must not rely on the behavior of ARM1176JZF-S processor for code that is intended to be ported to other ARM platforms.
Page 384 TCM and cacheable areas, but can be an issue for data. For example, in the following code: Loop LDR r0, [r2],#4 ; reads an item from D-TCM ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-13 ID012310 Non-Confidential, Unrestricted Access...
Page 385: Table 7-4 Summary Of Data Accesses To Tcm And Caches
No write to level two even if marked as if marked Cacheable. Write-Through. Miss Read from Data Cache. Write to Data Cache. If Write-Through, write to Instruction TCM. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-14 ID012310 Non-Confidential, Unrestricted Access...
Page 386: Table 7-5 Summary Of Instruction Accesses To Tcm And Caches
Miss Miss Don’t care If Cacheable and cache enabled, cache linefill. If Noncacheable or cache disabled, read to level two. a. Excludes unexpected hit. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-15 ID012310 Non-Confidential, Unrestricted Access...
Page 387: Write Buffer
8 word, 8 word aligned, block, and the address comparisons are based on 8 word aligned addresses. Memory access control on page 6-11 describes the ordering of memory accesses. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 7-16 ID012310 Non-Confidential, Unrestricted Access...
Page 388 Data Read/Write Interface transfers on page 8-15 • Peripheral Interface transfers on page 8-37 • Endianness on page 8-38 • Peripheral Interface transfers on page 8-37. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 389: Chapter 8 Level Two Interface
It is a key feature in ensuring high system performance, providing a higher bandwidth mechanism for filling the caches in a cache miss than has existed on previous ARM processors. The processor level two interconnect system uses the following 64-bit wide AXI interfaces: •...
Page 390: Table 8-1 Axi Parameters For The Level 2 Interconnect Interfaces
Noncacheable. The interface is optimized for cache linefills rather than individual requests. 8.1.3 Level two data-side controller The level two data-side controller is responsible for the level two: • Data Read/Write Interface • Peripheral Interface. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 391 The Peripheral Interface is a bidirectional AXI interface that services peripheral devices. In ARM1176JZF-S processors, the Peripheral Interface is used for peripherals that are private to the processor, such as the Vectored Interrupt Controller or Watchdog Timer. Accesses to regions of memory that are marked as Device and Non-Shared are routed to the Peripheral Interface in preference to the Data Read/Write Interface.
Page 392: Dma Interface
The size of the transfer is given in the parameters of the transfer in the CP15 registers. The transfers are always aligned with the size of the transfer as indicated by the CP15 registers. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 393: Synchronization Primitives
SWP and SWPB instructions. These support basic busy and free semaphore mechanisms. For details of the swap instructions, and how to use them to implement semaphores, see the ARM Architecture Reference Manual.
Page 394 ..; yes – we have the lock The typical case, where the lock is free and you have exclusive-access, is six instructions. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 395: Axi Control Signals In The Processor
Write channel Master Write Write Write Write Slave interface data data data data interface Write response channel Write response Figure 8-3 Channel architecture of writes ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 396 Write response channel The write response channel provides a way for the slave to respond to write transactions. All write transactions use completion signaling. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 397: Table 8-2 Axlen[3:0] Encoding
The AxLEN[3:0] signal indicates the number of transfers in a burst. Table 8-2 shows the values of AxLEN that the processor uses. Table 8-2 AxLEN[3:0] encoding AxLEN[3:0] Number of data transfers b0000 b0001 b0010 b0011 b0100 b0101 b0110 b0111 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-10 ID012310 Non-Confidential, Unrestricted Access...
Page 398: Table 8-3 Axsize[2:0] Encoding
Bytes in transfer b000 b001 b010 b011 AxBURST[1:0] The AxBURST[1:0] signals indicate a fixed, incrementing or wrapping burst. Table 8-4 shows the burst types that the ARM1176JZF-S processor supports. Table 8-4 AxBURST[1:0] encoding AxBURST[2:0] Burst type Description Fixed Fixed address burst...
Page 399: Table 8-6 Axcache[3:0] Encoding
AxPROT[2] 0 = Data access 1 = Instruction access AxPROT[1] 0 = Secure 1 = Non-secure AxPROT[0] 0 = Normal, User 1 = Privileged ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-12 ID012310 Non-Confidential, Unrestricted Access...
Page 400: Table 8-8 Axsideband[4:1] Encoding
Inner write-back, no allocate on write b1111 Inner write-back, write allocate a. The ARM1176JZF-S processor does not support write allocate. Table 8-9 shows the correspondence between the ARSIDEBANDI[4:1] encoding and the TLB cacheable attributes for the Instruction port. Table 8-9 ARSIDEBANDI[4:1] encoding...
Page 401: Instruction Fetch Interface Transfers
2 data transfers 0x14 0x14 , word 6 Incr 64-bit 1 data transfer 0x18 0x18 , word 7 Incr 64-bit 1 data transfer 0x1C 0x1C ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-14 ID012310 Non-Confidential, Unrestricted Access...
Page 402: Data Read/Write Interface Transfers
Wrap 64-bit 4 data transfers 0x08 0x0F 0x08 Wrap 64-bit 4 data transfers 0x10 0x17 0x10 Wrap 64-bit 4 data transfers 0x18 0x1F 0x18 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-15 ID012310 Non-Confidential, Unrestricted Access...
Page 403: Table 8-13 Noncacheable Ldrb
, byte 6 Incr 16-bit 1 data transfer 0x06 0x06 , byte 7 Incr 8-bit 1 data transfer 0x07 0x07 Incr 8-bit 1 data transfer 0x08 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-16 ID012310 Non-Confidential, Unrestricted Access...
Page 404: Table 8-15 Noncacheable Ldr Or Ldm1
1 data transfer 0x10 0x10 , word 5 Incr 32-bit 2 data transfers 0x14 0x14 , word 6 Incr 64-bit 1 data transfer 0x18 0x18 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-17 ID012310 Non-Confidential, Unrestricted Access...
Page 405: Noncacheable Ldrd Or Ldm2 From Word 7
Noncacheable LDM4s addressing words 0 to 4 are shown in: • Table 8-21 on page 8-19 for a load from Strongly Ordered or Device memory ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-18 ID012310 Non-Confidential, Unrestricted Access...
Page 406: Table 8-21 Noncacheable Ldm4, Strongly Ordered Or Device Memory
Table 8-24 on page 8-20 for a load from Strongly Ordered or Device memory • Table 8-25 on page 8-20 for a load from Noncacheable memory or when the cache is disabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-19 ID012310 Non-Confidential, Unrestricted Access...
Page 407: Table 8-24 Noncacheable Ldm5, Strongly Ordered Or Device Memory
3 data transfers 0x00 0x00 0x04 , word 1 0x04 Incr 32-bit 6 data transfers 0x08 , word 2 0x08 Incr 64-bit 3 data transfers ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-20 ID012310 Non-Confidential, Unrestricted Access...
Page 408: Table 8-28 Noncacheable Ldm6, Noncacheable Memory Or Cache Disabled
+ LDR from 0x00 0x0C , word 3 LDM5 from 0x0C + LDM2 from 0x00 0x10 , word 4 LDM4 from 0x10 + LDM3 from 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-21 ID012310 Non-Confidential, Unrestricted Access...
Page 409: Table 8-32 Noncacheable Ldm7 From Word 2, 3, 4, 5, 6, Or 7
+ LDM3 from 0x00 0x0C , word 3 LDM5 from 0x0C + LDM4 from 0x00 , word 4 LDM4 from + LDM5 from 0x10 0x10 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-22 ID012310 Non-Confidential, Unrestricted Access...
Page 410: Table 8-36 Noncacheable Ldm10
0x18 + LDM8 from 0x00 + LDR from 0x00 , word 7 LDR from + LDM8 from + LDM2 from 0x1C 0x1C 0x00 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-23 ID012310 Non-Confidential, Unrestricted Access...
Page 411: Table 8-38 Noncacheable Ldm12
, word 2 LDM6 from + LDM8 from 0x08 0x08 0x00 , word 3 LDM5 from + LDM8 from + LDR from 0x0C 0x0C 0x00 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-24 ID012310 Non-Confidential, Unrestricted Access...
Page 412: Table 8-41 Noncacheable Ldm15
+ LDM8 from + LDM6 from 0x18 0x18 0x00 0x00 , word 7 LDR from + LDM8 from + LDM7 from 0x1C 0x1C 0x00 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-25 ID012310 Non-Confidential, Unrestricted Access...
Page 413: Table 8-43 Half-Line Write-Back
Wrap 64-bit 4 data transfers 0x08 0x0F 0x08 Wrap 64-bit 4 data transfers 0x10 0x17 0x10 Wrap 64-bit 4 data transfers 0x18 0x1F 0x18 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-26 ID012310 Non-Confidential, Unrestricted Access...
Page 414: Table 8-45 Cacheable Write-Through Or Noncacheable Strb
1 data transfer b1100 0000 0x07 , byte 7 0x07 Incr 8-bit 1 data transfer b1000 0000 0x08 Incr 8-bit 1 data transfer b0000 0001 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-27 ID012310 Non-Confidential, Unrestricted Access...
Page 415: Table 8-47 Cacheable Write-Through Or Noncacheable Str Or Stm1
Table 8-48 on page 8-29 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and AWLENRW for STM2s to words 0 to 6 over the Data Read/Write Interface. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-28 ID012310 Non-Confidential, Unrestricted Access...
Page 416: Cacheable Write-Through Or Noncacheable Strd Or Stm2 To Words 0, 1, 2, 3, 4, 5, Or 6
Address[4:0] Operations , word 6 STM2 to + STR to 0x18 0x18 0x00 0x1C , word 7 STR to 0x1C + STM2 to 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-29 ID012310 Non-Confidential, Unrestricted Access...
Page 417: Cacheable Write-Through Or Noncacheable Stm4 To Word 0, 1, 2, 3, Or 4
Table 8-55 Cacheable Write-Through or Noncacheable STM5 to word 4, 5, 6, or 7 Address[4:0] Operations , word 4 STM4 to + STR to 0x10 0x10 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-30 ID012310 Non-Confidential, Unrestricted Access...
Page 418: Cacheable Write-Through Or Noncacheable Stm6 To Word 0, 1, Or 2
0x00 , word 0 0x00 Incr 32-bit 7 data transfers b0000 1111 0x04 , word 1 0x04 Incr 32-bit 7 data transfers b1111 0000 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-31 ID012310 Non-Confidential, Unrestricted Access...
Page 419: Cacheable Write-Through Or Noncacheable Stm7 To Word 2, 3, 4, 5, 6 Or 7
+ STR to 0x00 0x04 , word 1 STM7 to 0x04 + STM2 to 0x00 , word 2 STM6 to + STM3 to 0x08 0x08 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-32 ID012310 Non-Confidential, Unrestricted Access...
Page 420: Table 8-63 Cacheable Write-Through Or Noncacheable Stm10
+ STM8 to + STR to 0x18 0x18 0x00 0x00 , word 7 STR to 0x1C + STM8 to 0x00 + STM2 to 0x00 0x1C ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-33 ID012310 Non-Confidential, Unrestricted Access...
Page 421: Table 8-65 Cacheable Write-Through Or Noncacheable Stm12
+ STM8 to + STM3 to 0x18 0x18 0x00 0x00 , word 7 STR to + STM8 to + STM4 to 0x1C 0x1C 0x00 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-34 ID012310 Non-Confidential, Unrestricted Access...
Page 422: Table 8-67 Cacheable Write-Through Or Noncacheable Stm14
+ STM8 to + STM5 to 0x18 0x18 0x00 0x00 , word 7 STR to + STM8 to + STM6 to 0x1C 0x1C 0x00 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-35 ID012310 Non-Confidential, Unrestricted Access...
Page 423: Table 8-69 Cacheable Write-Through Or Noncacheable Stm16
+ STM8 to + STM6 to 0x18 0x18 0x00 0x00 , word 7 STR to + STM8 to + STM7 to 0x1C 0x1C 0x00 0x00 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-36 ID012310 Non-Confidential, Unrestricted Access...
Page 424: Peripheral Interface Transfers
1 data transfer b1000 0x0B The peripheral port can only do incrementing bursts of 2 data transfers maximum. It does not support unaligned accesses. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 8-37 ID012310 Non-Confidential, Unrestricted Access...
Page 425: Endianness
Level Two Interface Endianness ARM1176JZF-S processors can be configured in one of three endianness modes of operation using the U, B, and E bits of the CP15 c1 Control Register, see Mixed-endian access support on page 4-17. BE-8 refers to byte-invariant big-endian configuration on 16-bit, halfword, and 32-bit, word, quantities only.
Page 426: Locked Access
For ARM1176JZF-S processors, this implies that, in the case of an abort received on the read part of a SWP instruction, the Peripheral port or Data port issues a dummy write access with all byte strobes LOW at the same address as the read access and with AWLOCK = 00, normal transaction.
Page 427 • Clocking and resets with no IEM on page 9-3 • Clocking and resets with IEM on page 9-5 • Reset modes on page 9-10. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 428: Chapter 9 Clocking And Resets
The processor clocking and reset schemes depend on the, optional, implementation of IEM. This chapter gives details of the way that clocking and resets work for processors that implement IEM and for those that do not. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 429: Clocking And Resets With No Iem
Write Buffer. This prevents stalling while waiting for the Write Buffer to drain. Following that, a request is made to the AXI interface, and subsequently a transfer is ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 430: Figure 9-2 Read Latency With No Iem
The following reset signals are only used if IEM is implemented. Otherwise, these inputs are not connected to any logic internally, and you must connect them according to your design rules: ARESETIn • ARESETRWn • ARESETPn • ARESETDn. • ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 431: Clocking And Resets With Iem
ACLKENI signal must be held high accordingly. All clocks can be stopped indefinitely without loss of state. Figure 9-3 on page 9-6 shows the clocks for the processor with IEM. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 432: Figure 9-3 Processor Clocks With Iem
FIFO multiplexed out Synchronization over FIFOs drain FIFOs all empty Normal FIFO operation FIFOs closed to new data Normal FIFO operation Figure 9-4 Processor synchronization with IEM ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 433 Figure 9-5 on page 9-8 shows the latency that the IEM register slices add in a system with ACLK and CLKIN of the same frequency, but not synchronous. This example AXI system is zero-wait-state. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 434: Figure 9-5 Read Latency With Iem
The DBGnTRST signal is the DBGTAP reset. nPORESETIN The nPORESETIN signal is the power-on reset that initializes the CP14 debug logic. See CP14 registers reset on page 13-25 for details. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 435 ARESETIn, ARESETRWn, ARESETPn, ARESETDn Reset signals for the SoC part of the IEM register slices. All of these are active LOW signals that reset logic in the processor. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 436: Reset Modes
Figure 9-6 Power-on reset It is recommended that you assert the reset signals for at least three CLKIN cycles to ensure correct reset behavior. Adopting a three-cycle reset eases the integration of other ARM parts into the system, for example, ARM9TDMI-based designs.
Page 437 9.4.3 Processor reset A processor or warm reset initializes the majority of the ARM1176JZF-S processor, excluding the ARM1176JZF-S DBGTAP controller and the EmbeddedICE-RT logic. Processor reset is typically used for resetting a system that has been operating for some time, for example, watchdog reset.
Page 438: Chapter 10 Power Control
About power control on page 10-2 • Power management on page 10-3 • VFP shutdown on page 10-6 • Intelligent Energy Management on page 10-7. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 10-1 ID012310 Non-Confidential, Unrestricted Access...
Page 439: About Power Control
In the processor extensive use is also made of gated clocks and gates to disable inputs to unused functional blocks. Only the logic actively in use to perform a calculation consumes any dynamic power. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 10-2 ID012310 Non-Confidential, Unrestricted Access...
Page 440: Power Management
After the processor clocks have been stopped the signal STANDBYWFI is asserted to indicate that the processor is in Standby mode. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 10-3 ID012310 Non-Confidential, Unrestricted Access...
Page 441 Basic clamps are instantiated in the placeholder. They can be changed to explicit gates in the RAM power domain, or pull-down transistors that clamp the values when the core is powered down. For implementation details, see the ARM1176JZF-S and ARM1176JZ-S Implementation Guide.
Page 442 Strongly-Ordered accesses. The STANDBYWFI signal can also be used to signal to the Power Management Controller that the ARM1176JZF-S processor is ready to have its power state changed. STANDBYWFI is asserted in response to a Wait For Interrupt operation. Note The Power Management Controller must not power down any of the processor power domains unless STANDBYWFI is asserted.
Page 443: Vfp Shutdown
Power Control 10.3 VFP shutdown The blocks in the top level of the ARM1176JZF-S are: • A1176RAM , that includes all the RAMs • when you have an IEM implementation: — the four IEM register slices — placeholders for level shifters and clamps between all the blocks •...
Page 444: Intelligent Energy Management
Use of IEM on page 10-8 Note The ARM1176JZF-S processor is IEM enabled but the level of support for the technology depends on the specific implementation. For information on clocks and resets with IEM, see Clocking and resets with IEM on page 9-5.
Page 445: Chapter 11 Coprocessor Interface
SoC that contains an Intelligent Energy Controller (IEC ™ ). For example systems, see the Intelligent Energy Controller Technical Overview. IEM is functionally transparent to the user. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 10-8 ID012310 Non-Confidential, Unrestricted Access...
Page 446 Chapter 11 Coprocessor Interface This chapter describes the coprocessor interface of the ARM1176JZF-S processor. It contains the following sections: • About the coprocessor interface on page 11-2 • Coprocessor pipeline on page 11-3 • Token queue management on page 11-9 •...
Page 447: About The Coprocessor Interface
The processor supports the connection of on-chip coprocessors through an external coprocessor interface. All types of coprocessor instruction are supported. The ARM instruction set supports the connection of 16 coprocessors, numbered 0-15, to an ARM processor. In the processor, the following coprocessor numbers are reserved:...
Page 448: Coprocessor Pipeline
Coprocessors reject those instructions they cannot handle. Table 11-1 lists all the coprocessor instructions supported by the processor and gives a brief description of each. For more details of coprocessor instructions, see the ARM Architecture Reference Manual. Table 11-1 Coprocessor instructions...
Page 449: Table 11-2 Coprocessor Control Signals
Any information that the queue carries can also be read and acted on at the same time. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-4 ID012310...
Page 450: Figure 11-1 Core And Coprocessor Pipelines
Ex2 stage through the accept queue, that is also maintained by the core. This token indicates to the core if the coprocessor is accepting the instruction in its I stage, or bouncing it. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-5 ID012310 Non-Confidential, Unrestricted Access...
Page 451: Figure 11-3 Coprocessor Pipeline
Stages Ex3 to Ex5 are same as stage Ex2 (not shown) Enable Ex6 stage Decoded instruction Full Flags Ex6 stage control Stall Ex6 Figure 11-3 Coprocessor pipeline ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-6 ID012310 Non-Confidential, Unrestricted Access...
Page 452: Table 11-3 Pipeline Stage Update
Each time a tag is assigned to an instruction, the tag number is incremented modulo 16 to generate the next tag. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-7 ID012310 Non-Confidential, Unrestricted Access...
Page 453 This is explained in more detail in Flush operations on page 11-19. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-8 ID012310 Non-Confidential, Unrestricted Access...
Page 454: Token Queue Management
The output is always provided by the buffer containing the oldest data. This is buffer C if it is full, or buffer B or, if that is empty, buffer A. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-9 ID012310...
Page 455: Table 11-4 Addressing Of Queue Buffers
Three from buffer A. Because buffer A is being emptied by writing to buffer B, it can accept the value Four from the input. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-10 ID012310 Non-Confidential, Unrestricted Access...
Page 456: Figure 11-6 Queue Flushing
A less-than-or-equal-to comparison is used to identify tags that are to be flushed. If a tag in the pipeline later than the queue matches, the Flush all signal is asserted to clear the entire queue. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-11 ID012310...
Page 457: Token Queues
A. ACPINSTRT[3:0] This is the flush tag associated with the instruction in ACPINSTR, and must be clocked into the tag associated with buffer A. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-12 ID012310 Non-Confidential, Unrestricted Access...
Page 458 This is deasserted when the issue stage is passing an instruction on to the Ex1 stage, whether it has been accepted or not. Otherwise, the signal is asserted to indicate that no valid data are available. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-13 ID012310 Non-Confidential, Unrestricted Access...
Page 459 A flag, unless the queue is full, when it is ignored. The finish queue is read by the coprocessor Ex6 stage. It can retire a CDP instruction if the finish queue is not empty. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-14 ID012310 Non-Confidential, Unrestricted Access...
Page 460: Data Transfer
The other passes load data from the core to the coprocessor and requires no queue, only two pipeline registers. Figure 11-9 on page 11-16 shows instruction iteration for loads. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-15 ID012310 Non-Confidential, Unrestricted Access...
Page 461: Figure 11-9 Instruction Iteration For Loads
To achieve correct alignment of the load data with the load instruction in the coprocessor Ex6 stage, the data must be double buffered when they arrive at the coprocessor. Figure 11-10 on page 11-17 shows an example. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-16 ID012310 Non-Confidential, Unrestricted Access...
Page 462: Figure 11-10 Load Data Buffering
The iterated store instructions then pass down the pipeline but have no other use, except to act as place markers for flushes and cancels. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-17 ID012310...
Page 463 Because store instructions do not use the finish token queue they are retired as soon as they leave the Ex1 stage of the pipeline. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-18 ID012310 Non-Confidential, Unrestricted Access...
Page 464: Operations
A flush can be triggered by the core in any stage from issue to WBls inclusive. When this happens a broadcast signal is received by the coprocessor, passing it the tag associated with the instruction triggering the flush. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-19 ID012310 Non-Confidential, Unrestricted Access...
Page 465: Table 11-5 Retirement Conditions
Ex1 because no token is required in the finish queue • CDP instructions require a token in the finish queue ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-20 ID012310 Non-Confidential, Unrestricted Access...
Page 466 Coprocessor Interface • all load instructions must pick up data from the load pipeline • phantom load instructions retire unconditionally. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-21 ID012310 Non-Confidential, Unrestricted Access...
Page 467: Multiple Coprocessors
CPALENGTHHOLD and CPAACCEPTHOLD HIGH, and CPASTDATAV LOW, because the pipeline is empty at this point. The coprocessor can then start normal operation. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 11-22 ID012310 Non-Confidential, Unrestricted Access...
Page 468 About the processor VIC port on page 12-3 • Timing of the VIC port on page 12-5 • Interrupt entry flowchart on page 12-7. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 12-1 ID012310 Non-Confidential, Unrestricted Access...
Page 469: Chapter 12 Vectored Interrupt Controller Port
ARM Limited. The processor VIC port and the Peripheral Interface enable you to connect a PL192 VIC to the processor. See ARM PrimeCell Vectored Interrupt Controller (PL192) Technical Reference Manual for more details. ARM DDI 0301H Copyright ©...
Page 470: About The Processor Vic Port
ARM state instruction in the IRQ handler IRQACK is driven by the processor to indicate to an external VIC that the processor wants to read the IRQADDR input. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 12-3 ID012310 Non-Confidential, Unrestricted Access...
Page 471 12.2.2 Interrupt handler exit The software acknowledges an IRQ interrupt handler exit to a VIC by issuing a write to the vector address register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 12-4 ID012310 Non-Confidential, Unrestricted Access...
Page 472: Timing Of The Vic Port
When the processor samples IRQADDRV LOW, it knows it can sample the nIRQ input again. Therefore, if the VIC requires some time for deasserting nIRQ, it must ensure that IRQADDRV stays HIGH until nIRQ has been deasserted. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 12-5 ID012310 Non-Confidential, Unrestricted Access...
Page 473 Ignores the nIRQ signal while IRQADDRV is HIGH. This gives the VIC time to deassert the nIRQ signal if there is no higher priority interrupt pending. Ignores the nFIQ signal while IRQADDRV is HIGH. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 12-6 ID012310 Non-Confidential, Unrestricted Access...
Page 474: Interrupt Entry Flowchart
NSBA + 0x1C SBA + 0x1C 0xFFFF001C MBA + 0x1C MBA + 0x18 0xFFFF0018 SBA + 0x18 NSBA + 0x18 0b00 Figure 12-3 Interrupt entry sequence ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 12-7 ID012310 Non-Confidential, Unrestricted Access...
Page 475 Debugging in a system with TLBs on page 13-44 • Monitor debug-mode debugging on page 13-45 • Halting debug-mode debugging on page 13-50 • External signals on page 13-52. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-1 ID012310 Non-Confidential, Unrestricted Access...
Page 476: Chapter 13 Debug
• resume program execution. The debug host and the protocol converter are system-dependent. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-2 ID012310 Non-Confidential, Unrestricted Access...
Page 477: About The Debug Unit
The state of the processor is preserved in the same manner as all ARM exceptions. See the ARM Architecture Reference Manual on exceptions and exception priorities. The debug monitor target communicates with the debugger to access processor and coprocessor state, and to access memory contents and input/output peripherals.
Page 478 Virtual addresses and debug Unless otherwise stated, all addresses in this chapter are Modified Virtual Addresses (MVA) as the ARM Architecture Reference Manual describes. For example, the Breakpoint Value Registers (BVR) and Watchpoint Value Registers (WVR) must be programmed with MVAs.
Page 479: Debug Registers
Opcode_2 b000 b0000 Debug ID Register DIDR b000 b0001 Debug Status and Control Register DSCR b000 b0010-b0100 c2-c4 Reserved b000 b0101 Data Transfer Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-5 ID012310 Non-Confidential, Unrestricted Access...
Page 480: Figure 13-2 Debug Id Register Format
Context Version UNP/SBZ Variant Revision Debug architecture revision Figure 13-2 Debug ID Register format For the ARM1176JZF-S processor: • DIDR[31:8] has the value 0x15121x ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-6 ID012310 Non-Confidential, Unrestricted Access...
Page 481: Table 13-3 Debug Id Register Bit Field Definition
= 1 WRP b0001 = 2 WRPs … b1111 = 16 WRPs. For the ARM1176JZF-S processor these bits are b0001 (2 WRPs). [27: 24] Number of Breakpoint Register Pairs: b0000 = Reserved. The minimum number of BRPs is 2.
Page 482: Table 13-4 Debug Status And Control Register Bit Field Definitions
Debug state. When set, the core does not act on imprecise data aborts. However, the sticky imprecise data abort bit is set if an imprecise data abort occurs when in Debug state. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-8 ID012310 Non-Confidential, Unrestricted Access...
Page 483 0 = Disabled 1 = Enabled. If this bit is set, the core can be forced to execute ARM instructions in Debug state using the Debug Test Access Port. If this bit is set when the core is not in Debug state, the behavior of the processor is architecturally Unpredictable.
Page 484 This flag is meant to detect Data Aborts generated by instructions issued to the processor using the Debug Test Access Port. Therefore, if the DSCR[13] execute ARM instruction enable bit is a 0, the value of the sticky precise Data Abort bit is architecturally Unpredictable.
Page 485 CP14 c5, Data Transfer Registers (DTR) This register consists of two separate physical registers: • the rDTR, Read Data Transfer Register • the wDTR, Write Data Transfer Register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-11 ID012310 Non-Confidential, Unrestricted Access...
Page 486: Table 13-5 Data Transfer Register Bit Field Definitions
• accessible in privileged modes only. When a watchpoint occurs in: • ARM state, the WFAR contains the address of the instruction causing it plus • Thumb state, the WFAR contains the address of the instruction causing it plus •...
Page 487: Figure 13-5 Vector Catch Register Format
Table 13-6 on page 13-14 lists the bit field definitions for the Vector Catch Register. In Table 13-6 on page 13-14, SBA means Secure Base Address, NSBA means Non-secure Base Address, MBA means Monitor Base Address. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-13 ID012310 Non-Confidential, Unrestricted Access...
Page 488: Table 13-6 Vector Catch Register Bit Field Definitions
Table 13-7 Summary of debug entry and exception conditions VCR bit NS bit, mode HIVECS Prefetch vector VCR[0] = 1 NS bit = 0 or Mode = Secure 0x00000000 Monitor. 0xFFFF0000 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-14 ID012310 Non-Confidential, Unrestricted Access...
Page 489 VCR[27] = 1 NSBA + 0x0000000C Monitor 0xFFFF000C NS bit = 1 and mode ≠ Secure VCR[28] = 1 NSBA + 0x00000010 Monitor 0xFFFF0010 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-15 ID012310 Non-Confidential, Unrestricted Access...
Page 490: Table 13-8 Processor Breakpoint And Watchpoint Registers
Monitor debug-mode, it is ignored. This is to avoid the processor ending in an unrecoverable state. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-16 ID012310...
Page 491: Table 13-9 Breakpoint Value Registers, Bit Field Definition
5 4 3 2 1 0 Byte UNP/ UNP/SBZP E Linked BRP UNP/SBZP address select Secure breakpoint match Figure 13-6 Breakpoint Control Registers, format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-17 ID012310 Non-Confidential, Unrestricted Access...
Page 492: Table 13-11 Breakpoint Control Registers, Bit Field Definitions
Linked BRP number. The binary number encoded here indicates another BRP to link this one with. If a BRP is linked with itself, it is architecturally Unpredictable if a breakpoint debug event is generated. For ARM1176JZF-S processors the breakpoint debug event is not generated.
Page 493: Table 13-12 Meaning Of Bcr[22:20] Bits
ID comparison. See Setting breakpoints, watchpoints, and vector catch debug events on page 13-45 for detailed programming sequences for linked breakpoints and linked watchpoints. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-19 ID012310 Non-Confidential, Unrestricted Access...
Page 494: Table 13-13 Processor Watchpoint Value Registers
If a BRP, holding an IMVA, is linked with one that is not configured for context ID comparison and linking, it is architecturally Unpredictable whether a breakpoint debug event is generated or not. For ARM1176JZF-S processors the breakpoint debug event is not generated. BCR[22:20] fields of the second BRP must be set to b011.
Page 495: Table 13-14 Watchpoint Value Registers, Bit Field Definitions
BRP field. [19:16] Linked BRP. The binary number encoded here indicates a context ID holding BRP to link this WRP with. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-21 ID012310 Non-Confidential, Unrestricted Access...
Page 496 The update of a WVR or a WCR can take effect several instructions after the corresponding MCR. It only guaranteed to have taken effect by the next IMB. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-22 ID012310...
Page 497: Table 13-17 Debug State Cache Control Register Bit Functions
BRP must be set to b011. • If a WRP is linked with a BRP that is not implemented, it is architecturally Unpredictable if a watchpoint debug event is generated or not. For ARM1176JZF-S processors the watchpoint debug event is not generated. •...
Page 498: Table 13-18 Debug State Mmu Control Register Bit Functions
1 = Normal operation of Data Micro TLB loading and flushing in Debug state. 0 = Data Micro TLB load and flush disabled in Debug state. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-24 ID012310 Non-Confidential, Unrestricted Access...
Page 499: Cp14 Registers Reset
It also ensure that the DBGTAP debugger can be connected when the processor is running without clearing CP14 debug setting, because DBGnTRST does not reset these registers. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-25 ID012310...
Page 500: Cp14 Debug Instructions
112-127 MRC p14, 0, <Rd>, c0, cy, 7 MCR p14, 0, <Rd>, c0, cy, 7 a. <Rd> is any of R0-R14 ARM registers. b. y is the decimal representation for the binary number CRm. In Table 13-19, refer to the rDTR MRC p14,0,<Rd>,c0,c5,0...
Page 501: Table 13-20 Debug Instruction Execution
Proceed Proceed Undefined exception Privileged b01, Halting Proceed Proceed Undefined exception Privileged b10, Monitor Proceed Proceed Proceed Privileged b11, Halting Proceed Proceed Undefined exception ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-27 ID012310 Non-Confidential, Unrestricted Access...
Page 502: External Debug Interface
Not permitted in Secure Monitor state. permitted Debug not Not permitted in Secure state. permitted not Secure No debug mode Permitted in Non-secure Monitor state. selected ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-28 ID012310 Non-Confidential, Unrestricted Access...
Page 503 User Debug not Not permitted in privileged modes in Secure state. permitted User Halting Permitted in User mode in debug-mode Secure state. Capabilities restricted. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-29 ID012310 Non-Confidential, Unrestricted Access...
Page 504 Behavior of the processor on debug events on page 13-33 describes the behavior marked as not permitted. Logically, the processor is still configured for either Halting debug-mode or Monitor debug-mode, as appropriate. c. Debug exceptions are handled in a privileged mode. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-30 ID012310 Non-Confidential, Unrestricted Access...
Page 505: Changing The Debug Enable Signals
LOW, DSCR[15:14] read as zero, and therefore the view that the processor has of DBGEN can be polled by writing to DSCR[15:14] and using the value read back to determine its setting. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-31 ID012310...
Page 506: Debug Events
When this happens, the DSCR[5:2] method of entry bits are set to b0100.This signal can be driven by the ETM to signal a trigger to the core. For example, if a memory permission ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-32 ID012310...
Page 507: Table 13-22 Behavior Of The Processor On Debug Events
Monitor debug-mode is selected and enabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-33 ID012310 Non-Confidential, Unrestricted Access...
Page 508: Table 13-23 Setting Of Cp15 Registers On Debug Events
R14_abt, SPRS_abt and the CP15 registers listed in this section, leading to an unpredictable software behavior if the handlers did not have the chance of saving the registers. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-34 ID012310...
Page 509: Debug Exception
The address of the instruction causing the Software debug event plus can be found in the 0x04 R14_abt register. Table 13-24 on page 13-36 lists the values in the link register after exceptions. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-35 ID012310 Non-Confidential, Unrestricted Access...
Page 510: Table 13-24 Values In The Link Register After Exceptions
RA is not the address of the instruction immediately after the one that hit the watchpoint, the processor might stop a number of instructions later. The address of the instruction that hit the watchpoint is in the CP15 WFAR. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-36 ID012310...
Page 511: 13.10 Debug State
ARM state instruction. This mechanism is enabled using DSCR[13] execute ARM instruction enable bit. • The core executes the instruction as if it is in ARM state, regardless of the actual value of the T and J bits of the CPSR. •...
Page 512 In Debug state: • The PC is frozen on entry to Debug state. That is, it does not increment on the execution of ARM instructions. However, branches and instructions that modify the PC directly do update it. ARM DDI 0301H Copyright ©...
Page 513: Table 13-25 Read Pc Value After Debug State Entry
However, the CPSR has to be set to the return ARM, Thumb, or Jazelle state before the PC is written to, otherwise the processor behavior is Unpredictable.
Page 514 Barrier operation to flush all pending memory operations to the system. Once these operations have completed, the processor sets DSCR[19]. If any of these operations cause imprecise data ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-40 ID012310...
Page 515: Table 13-26 Example Memory Operation Sequence
The previous abort latched on row (3) is taken, now the processor has left Debug state and the A bit in the CPSR is not set. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-41 ID012310...
Page 516: 13.11 Debug Communications Channel
• The mechanism for forcing the core to execute ARM instructions, when the core is in Debug state. For details see Executing instructions in Debug state on page 14-21. At the core side, the debug communications channel resources are: •...
Page 517: 13.12 Debugging In A Cached System
Cache, that c7, Cache operations on page 3-69 describes, to ensure that, after a write, there are no out-of-date words in the Instruction Cache. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-43 ID012310 Non-Confidential, Unrestricted Access...
Page 518: 13.13 Debugging In A System With Tlbs
TLBs in this mode using CP14 c11. See CP14 c11, Debug State MMU Control Register on page 13-23. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-44 ID012310 Non-Confidential, Unrestricted Access...
Page 519: 13.14 Monitor Debug-Mode Debugging
Read the BCR. Clear the BCR[0] enable breakpoint bit in the read word and write it back to the BCR. Now the breakpoint is disabled. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-45 ID012310 Non-Confidential, Unrestricted Access...
Page 520 Clear the BCRa[0] and BCRb[0] enable breakpoint bits in the read words and write them back to the BCRs. Now the breakpoints are disabled. Write the IMVA to the BVRa register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-46 ID012310 Non-Confidential, Unrestricted Access...
Page 521 In the following sequence b is any of the BRPs with context ID comparison capability. You can use any of the WRPs. You can link WRPs and contextID-holding BRPs as follows: Read the WCR and BCRb. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-47 ID012310 Non-Confidential, Unrestricted Access...
Page 522 If DSCR[30] rDTRfull flag is clear, then go to 1. Read the word from the rDTR, CP14 Debug Register c5. To write a word for a DBGTAP debugger: Read the DSCR register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-48 ID012310 Non-Confidential, Unrestricted Access...
Page 523 Debug If DSCR[29] wDTRfull flag is set, then go to 1. Write the word to the wDTR, CP14 Debug Register c5. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-49 ID012310 Non-Confidential, Unrestricted Access...
Page 524: 13.15 Halting Debug-Mode Debugging
13-45. The only difference is that the CP14 debug registers are accessed using the DBGTAP scan chains, see The DBGTAP port and debug registers on page 14-6. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-50 ID012310 Non-Confidential, Unrestricted Access...
Page 525 Note A DBGTAP debugger can access the CP14 debug registers whether the processor is in Debug state or not, so these debug events can be programmed while the processor is in ARM, Thumb, or Jazelle state. Setting software breakpoints (BKPT) To set a software breakpoint, the DBGTAP debugger must perform the same steps as the debug monitor target.
Page 526: 13.16 External Signals
13-4 describes. SPNIDEN Secure Privileged Non-invasive Debug Enable input signal, as Secure Monitor mode and debug on page 13-4 describes. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 13-52 ID012310 Non-Confidential, Unrestricted Access...
Page 527 Using the Debug Test Access Port on page 14-21 • Debug sequences on page 14-29 • Programming debug events on page 14-40 • Monitor debug-mode debugging on page 14-42. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-1 ID012310 Non-Confidential, Unrestricted Access...
Page 528: Debug Test Access Port And Debug State
Update-IR Update-DR tms=1 tms=0 tms=1 tms=0 Figure 14-1 JTAG DBGTAP state machine diagram 1. From IEEE Std 1149.1-2001. Copyright 2001 IEEE. All rights reserved. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-2 ID012310 Non-Confidential, Unrestricted Access...
Page 529: Synchronizing Realview Ice
14.2 Synchronizing RealView ICE The system and test clocks are synchronized internally to the macrocell. The ARM RealView ICE debug agent directly supports one or more cores within an ASIC design. The off-chip device, for example, RealView ICE, issues a TCK signal and waits for the RTCK, Returned TCK, signal to come back.
Page 530: Entering Debug State
• all instructions are read from the instruction transfer register, scan chain 4. Debug state on page 13-37 describes the Debug state. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-4 ID012310 Non-Confidential, Unrestricted Access...
Page 531: Exiting Debug State
When Run-Test/Idle state is entered, all the processors resume operation simultaneously. The core restarted bit is set when the Restart sequence is complete. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-5 ID012310 Non-Confidential, Unrestricted Access...
Page 532: The Dbgtap Port And Debug Registers
When the instruction register is loaded with the INTEST instruction, the debug scan chains can be read. See Scan chains on page 14-10. b01101-b11100 Reserved. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-6 ID012310 Non-Confidential, Unrestricted Access...
Page 533 Sample/Preload, Clamp, HighZ, and ClampZ instructions are not implemented because the processor DBGTAP controller does not support the attachment of external boundary scan chains. All unused DBGTAP controller instructions default to the Bypass instruction. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-7 ID012310 Non-Confidential, Unrestricted Access...
Page 534: Debug Registers
ID fields are routed to the edge of the chip so that partners can create their own Device ID numbers by tying the pins to HIGH or LOW values. The default manufacturer ID for the ARM1176JZF-S processor is b11110000111. The part number field is hard-wired inside the ARM1176JZF-S to...
Page 535: Figure 14-4 Device Id Code Register Bit Order
Debug Test Access Port All ARM semiconductor partner-specific devices must be identified by manufacturer ID numbers of the form shown in c0, Main ID Register on page 3-20. Length 32 bits. Operating mode When the ID code instruction is current, the shift section of the device ID register is selected as the serial path between DBGTDI and DBGTDO.
Page 536: Figure 14-6 Scan Chain Select Register Bit Order
Capture-DR state. The previous value of the scan chain is shifted out during the Shift-DR state, while a new value is shifted in. The scan chain is updated with the new value during Update-DR. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-10 ID012310 Non-Confidential, Unrestricted Access...
Page 537: Figure 14-7 Scan Chain 0 Bit Order
This field is hardwired to 0x41 , the implementor code for ARM Limited, as specified in the ARM Architecture Reference Manual. This register is read-only. Therefore, EXTEST has the same effect as INTEST. Order Figure 14-7 shows the order of bits in scan chain 0.
Page 538 DSCR[6] Sticky precise Data Abort flag. If the core is in Debug state and the DSCR[13] execute ARM instruction enable bit is HIGH, then this flag is set on precise Data Aborts. See CP14 c1, Debug Status and Control Register (DSCR) on page 13-7.
Page 539: Figure 14-9 Scan Chain 4 Bit Order
• The processor must be in Debug state. • The DSCR[13] execute ARM instruction enable bit must be set. For details of the DSCR see CP14 c1, Debug Status and Control Register (DSCR) on page 13-7. •...
Page 540 DBGTAP debugger must set up the data in the rDTR before issuing the coprocessor instruction to the core. See Scan chain 5 on page 14-15. • Setting DSCR[13] the execute ARM instruction enable bit when the core is not in Debug state leads to Unpredictable behavior. •...
Page 541: Figure 14-10 Scan Chain 5 Bit Order, Extest Selected
As part of the Debug Communications Channel (DCC). The DBGTAP debugger uses scan chain 5 to exchange data with software running on the core. The software accesses the rDTR and wDTR using coprocessor instructions. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-15 ID012310 Non-Confidential, Unrestricted Access...
Page 542 InstCompl flags when the core changes state is as follows: • The DSCR[13] execute ARM instruction enable bit must be clear when the core is not in Debug state. Otherwise, the behavior of the rDTR and wDTR registers, and the flags, is Unpredictable.
Page 543: Figure 14-12 Scan Chain 6 Bit Order
Debug Test Access Port • The InstCompl flag must be set when the DSCR[13] execute ARM instruction enable bit is changed from 1 to 0. Otherwise, the behavior of the core is Unpredictable. If the DSCR[13] flag is cleared correctly, none of the registers and flags are altered.
Page 544: Figure 14-13 Scan Chain 7 Bit Order
Scan in the address of a first register and a 0 to indicate that this is a read request. The Data field is not important. Scan in the address of a second register and a 0 to indicate that this is a read request. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-18 ID012310 Non-Confidential, Unrestricted Access...
Page 545: Table 14-2 Scan Chain 7 Register Map
This implies that breakpoints, watchpoints, and vector traps can be programmed through the Debug Test Access Port even if the processor is running. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-19 ID012310 Non-Confidential, Unrestricted Access...
Page 546 • If a read request to the PC completes and Data[1:0] equals b00, the read value corresponds to an ARM state instruction whose 30 most significant bits of the offset address, instruction address + 8, are given in Data[31:2]. •...
Page 547: Using The Debug Test Access Port
14.7.2 Executing instructions in Debug state When the processor is in Debug state, it can be forced to execute ARM state instructions using the DBGTAP. Two registers are used for this purpose, the Instruction Transfer Register (ITR) and the Data Transfer Register (DTR). The ITR is used to insert an instruction into the processor pipeline.
Page 548: Figure 14-14 Behavior Of The Itrsel Ir Instruction
Figure 14-14 Behavior of the ITRsel IR instruction Consider for example the preceding sequence to store out the contents of ARM register R0. This is the same sequence using the ITRsel instruction: Scan_N into the IR. 1 into the SCREG.
Page 549 DTR comprises both a read, rDTR, and a write portion, wDTR, a piece of data written by the core and another coming from the DBGTAP debugger can be held in this register at the same time. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-23 ID012310 Non-Confidential, Unrestricted Access...
Page 550 Scan in 34 bits, the least significant 32 holding the word to be sent. At the same time, 34 bits were scanned out. If the nRetry flag is clear, repeat this step again. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-24 ID012310...
Page 551 14-21 describes in addition to scan chain 5. You must ensure that the DSCR[13] execute ARM instruction enable bit is set for the instruction execution mechanism to work. When it is set, the interface for the DBGTAP debugger consists of the following: •...
Page 552 Target to host transfer The DBGTAP debugger can use the following sequence for reading data from the processor memory system. The sequence assumes that the ARM register R0 contains a pointer to the address of memory where the read has to start: Scan_N into the IR.
Page 553 Host to target transfer The DBGTAP debugger can use the following sequence for writing data to the processor memory system. The sequence assumes that the ARM register R0 contains a pointer to the address of memory where the write has to start: Scan_N into the IR.
Page 554 If the sticky imprecise Data Abort flag is set, an imprecise Data Abort has occurred and the sequence restarts at step 1 after the cause of the abort is fixed and c0 is reloaded. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-28 ID012310...
Page 555: Debug Sequences
Go to the DBGTAP controller Run-Test/Idle state so that the processor exits Debug state. INST <instr> [stateout] Go through Capture-DR, go to Shift-DR, scan in an ARM instruction to be read and executed by the core and scan out the Ready flag, go through Update-DR. The ITR, scan chain 4, and EXTEST must be selected when using this macro.
Page 556 • The contents of wDTR[31:0], to be stored in dataout. • If the DSCR[13] execute ARM instruction enable bit is set, the value of the Ready flag is stored in stateout. • If the DSCR[13] execute ARM instruction enable bit is clear, the nRetry or Valid flag, depending on whether EXTEST or INTEST is selected, is stored in stateout.
Page 557 ; select DTR INTEST DATA 0x00000000 Valid wDTR If Valid==1 then Save value in wDTR Set the DSCR[13] execute ARM instruction enable bit, so instructions can be issued to the core from now: SCAN_N 1 ; select DSCR EXTEST DATA modifiedDSCR ;...
Page 558 ; clears DSCR[7] Store out R0. It is going to be used to save the rDTR. Use the standard sequence of Reading a current mode ARM register in the range R0-R14 on page 14-34. Scan chain 5 and INTEST are now selected.
Page 559 R0 as a temporary register, in two steps. Load the saved wDTR contents into R0 using the standard sequence of Writing a current mode ARM register in the range R0-R14 on page 14-34. Now scan chain 5 and EXTEST are selected...
Page 560 Debug Test Access Port 14.8.6 Reading a current mode ARM register in the range R0-R14 Use the following sequence to read a current mode ARM register in the range R0-R14: SCAN_N ; select DTR ITRSEL ; select the ITR and EXTEST...
Page 561 UNTIL Ready==1 ; wait until the instruction ends Perform the read of R0 using the standard sequence that Reading a current mode ARM register in the range R0-R14 on page 14-34 describes. Scan chain 5 and ITRsel are already selected.
Page 562 Here R0 is used as a temporary register: Load R0 with the address to resume using the standard sequence that Writing a current mode ARM register in the range R0-R14 on page 14-34 describes. Now scan chain 5 and EXTEST are selected.
Page 563 UNTIL Ready==1 ; wait until instruction ends ENDFOR INTEST ; deselect the DTR Wait for the last write to finish: LOOP DATA 0x00000000 Ready ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-37 ID012310 Non-Confidential, Unrestricted Access...
Page 564 Two operations are required to complete a halfword or byte transfer, from memory to ARM register and from ARM register to CP14 debug register. Therefore, performance is decreased because the load instruction cannot be kept in the ITR. This sequence assumes that R0 has been set to the address to load data from prior to running the sequence.
Page 565 INST 0x00000000 Ready UNTIL Ready==1 ; wait until instruction ends Use the standard sequence that Reading a current mode ARM register in the range R0-R14 on page 14-34 describes. 14.8.19 Writing coprocessor registers Write the value onto R0, using the standard sequence. See Writing a current mode ARM register in the range R0-R14 on page 14-34 for more details.
Page 566: Programming Debug Events
An External Debugger can access the CP14 debug registers whether the processor is in Debug state or not, so these debug events can be programmed on-the-fly, while the processor is in ARM/Thumb/Jazelle state. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-40 ID012310 Non-Confidential, Unrestricted Access...
Page 567 All of these can be done using the previously described sequences. Note Cache coherency issues might arise when writing a BKPT instruction. See Debugging in a cached system on page 13-43. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-41 ID012310 Non-Confidential, Unrestricted Access...
Page 568: 14.10 Monitor Debug-Mode Debugging
14.10.2 Sending data to the core SCAN_N 5 ; select DTR EXTEST FOREACH Data2Write LOOP DATA Data2Write nRetry UNTIL nRetry==1 ; wait until instruction ends ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 14-42 ID012310 Non-Confidential, Unrestricted Access...
Page 569: Chapter 15 Trace Interface Port
This chapter describes the Embedded Trace Macrocell (ETM) support for the processor. It contains the following section: • About the ETM interface on page 15-2. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 15-1 ID012310 Non-Confidential, Unrestricted Access...
Page 570: About The Etm Interface
15.1 About the ETM interface The processor trace interface port enables connection of an ETM to the processor. The ARM Embedded Trace Macrocell (ETM) provides instruction and data trace for the ARM11 family of processors. For more details on how the ETM interface connects to an ARM11 processor, see the CoreSight ETM11 Technical Reference Manual.
Page 571: Table 15-2 Etmiactl[17:0]
The exception signals become valid when the core takes the exception and remain valid until the next instruction is seen at the exception vector. Exception reporting The ARM1176JZF-S Trace Interface Port is designed for ETMs that support ETMv3.2 or above. ETMv3.2 permits the determination of each type of exception without reference to the destination address in the branch packet.
Page 572: Table 15-3 Etmiasecctl[1:0]
Table 15-4 Data address interface signals Signal name Description Qualified by ETMDACTL[17:0 Data address interface control signals ETMDA[31:3] DASlot != 00 AND !DACPRT Address for data transfer ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 15-4 ID012310 Non-Confidential, Unrestricted Access...
Page 573: Table 15-5 Etmdactl[17:0]
The data transfer is a CPRT. DASwizzle DASlot != 00 [14] Words must be byte swizzled for ARM big-endian mode. During an unaligned access, this signal is only valid on the first transfer of the access. DARot DASlot != 00 [13:12] Number of bytes to rotate right each word by.
Page 574: Table 15-6 Data Value Interface Signals
This interface enables an ETM to monitor a sub-set of CP14 and CP15 operations. Rather than using the external coprocessor interface, the core provides a dedicated, cut-down coprocessor interface similar to that used by the debug logic. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 15-6 ID012310 Non-Confidential, Unrestricted Access...
Page 575: Table 15-9 Coprocessor Interface Signals
Trace prohibited Non-secure access Figure 15-1 shows the format of the ETMCPADDRESS[14:0] signals. 12 11 4 3 2 Opcode Opcode Figure 15-1 ETMCPADDRESS format ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 15-7 ID012310 Non-Confidential, Unrestricted Access...
Page 576: Table 15-11 Other Connections
3-133 and the CoreSight ETM11 Technical Reference Manual. ETMPWRUP Input Indicates that the ETM is active. When LOW the Trace Interface must be clock gated to conserve power. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 15-8 ID012310 Non-Confidential, Unrestricted Access...
Page 577: Chapter 16 Cycle Timings And Interlock Behavior
Chapter 16 Cycle Timings and Interlock Behavior This chapter describes the cycle timings and interlock behavior of integer instructions on the ARM1176JZF-S processor. This chapter contains the following sections: • About cycle timings and interlock behavior on page 16-2 •...
Page 578: About Cycle Timings And Interlock Behavior
Iss stage of the main pipeline. The return stack mispredicts if the value taken from the return stack is not the value that is returned by the instruction. Only unconditional returns are ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-2 ID012310...
Page 579: Table 16-1 Pipeline Stages
Early Reg. The following sequence, requiring an Early Reg, takes five cycles: LDR R1, [R2] ;Result latency three plus one ADD R3, R3, R1 LSL#6 ;plus one because Register R1 is required by Sh ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-3 ID012310 Non-Confidential, Unrestricted Access...
Page 580: Conditional Instructions
If instruction A and instruction B both write the same register the pipeline must ensure that the register is written in the correct order. Therefore, interlocks might be required to correctly resolve this pipeline hazard. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-4 ID012310 Non-Confidential, Unrestricted Access...
Page 581: Table 16-2 Definition Of Cycle Timing Terms
Subtract one cycle from the result latency of the instruction producing this register for interlock calculations. FlagsCycleDistance The number of cycles between an instruction that sets the flags and the conditional instruction. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-5 ID012310 Non-Confidential, Unrestricted Access...
Page 582: Register Interlock Examples
LDR R1, [R2] Takes five cycles because of the result latency and the use of the result of R1 as an Early Reg LDR R5, [R1] ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-6 ID012310 Non-Confidential, Unrestricted Access...
Page 583: Data Processing Instructions
Conditional MOV to PC, no MOV <cond> pc, <Rd> shift required Conditional MOV to PC, with a MOV pc, <Rn>, <Rm>, LSL #<immed> <Rm> shifted source register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-7 ID012310 Non-Confidential, Unrestricted Access...
Page 584 For example, the following sequence takes four cycles to execute: ADD R1, R2, R3 ADD R4, R2, R4, LSL R1 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-8 ID012310 Non-Confidential, Unrestricted Access...
Page 585: Qadd, Qdadd, Qsub, And Qdsub Instructions
Table 16-6 lists the cycle timing behavior for QADD, QDADD, QSUB, and QDSUB instructions. Table 16-6 QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior Cycle Instructions Early Reg Result latency QADD, QSUB QDADD, QDSUB <Rn> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-9 ID012310 Non-Confidential, Unrestricted Access...
Page 586: Armv6 Media Data-Processing
UADD8TO16, UADD8TO32, UADD16TO32 <Rm> REV, REV16, REVSH <Rm> PKHBT, PKHTB <Rm> SSAT, USAT <Rm> QADDSUBX, QSUBADDX <Rm> SHADDSUBX, SHSUBADDX <Rm> UQADDSUBX, UQSUBADDX <Rm> UHADDSUBX, UHSUBADDX <Rm> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-10 ID012310 Non-Confidential, Unrestricted Access...
Page 587: Armv6 Sum Of Absolute Differences (Sad)
Takes three cycles. The Result latency is one less because the result is used as the USADA8 R1,R4,R5,R1 accumulate for a subsequent USADA8 instruction. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-11 ID012310 Non-Confidential, Unrestricted Access...
Page 588: Multiplies
SMMLA, SMMLAR <Rm>, <Rs> <Rn> SMMLS, SMMLSR <Rm>, <Rs> <Rn> SMLALD, SMLALDX <Rm>, <Rs> <RdHi> SMLSLD, SMLSLDX <Rm>, <Rs> <RdHi> UMAAL <Rm>, <Rs> <RdLo> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-12 ID012310 Non-Confidential, Unrestricted Access...
Page 589 Cycle Timings and Interlock Behavior Note Result latency is one less if the result is used as the accumulate register for a subsequent multiply accumulate. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-13 ID012310 Non-Confidential, Unrestricted Access...
Page 590: Branches
The timing behavior is: Cycle = MAX (MaxCycles - FlagCycleDistance, MinCycles). ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-14 ID012310 Non-Confidential, Unrestricted Access...
Page 591: Processor State Updating Instructions
All other MSRs to the CPSR MSR SPSR All MSRs to the SPSR CPS <effect> <iflags> Interrupt masks only CPS <effect> <iflags>, #<mode> Mode changing SETEND ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-15 ID012310 Non-Confidential, Unrestricted Access...
Page 592: 16.10 Single Load And Store Instructions
ARMv6 unaligned access LDR <Rd>, <addr_md_1cycle> ARMv6 unaligned access LDR <Rd>, <addr_md_2cycle> a. See Table 16-15 on page 16-17 for an explanation of <addr_md_1cycle> <addr_md_2cycle> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-16 ID012310 Non-Confidential, Unrestricted Access...
Page 593: Table 16-14 Cycle Timing Behavior For Loads To The Pc
LDR <Rd>, [<Rn>, <Rm>, LSL #2] (!) <Rn>, <Rm> LDR <Rd>, [<Rn>], #cns <Rn> LDR <Rd>, [<Rn>], <Rm> <Rn>, <Rm> LDR <Rd>, [<Rn>], <Rm>, LSL #2 <Rn>, <Rm> <addr_md_2cycle> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-17 ID012310 Non-Confidential, Unrestricted Access...
Page 594 ADD stage. For example, the following instruction sequence take three cycles to execute: LDR R5, [R2, #4]! LDR R6, [R2, #0x10]! LDR R7, [R2, #0x20]! ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-18 ID012310 Non-Confidential, Unrestricted Access...
Page 595: 16.11 Load And Store Double Instructions
Table 16-17 lists the explanation of <addr_md_1cycle> <addr_md_2cycle> that Table 16-16 uses. Table 16-17 <addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction explanation Example instruction Early Reg Comment <addr_md_1cycle> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-19 ID012310 Non-Confidential, Unrestricted Access...
Page 596 If negative register offset, or shift other than LSL #2 then two-issue cycles. LDRD Rd, [<Rm>, -<Rm> <shf> <cns>] (!) <Rm> LDRD <Rd>, [<Rn>], -<Rm> <Rm> LDRD< Rd>, [Rn], -<Rm> <shf> <cns> <Rm> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-20 ID012310 Non-Confidential, Unrestricted Access...
Page 597: 16.12 Load And Store Multiple Instructions
LDMIA Rx,{R1} LDMIA Rx,{R1,R2} LDMIA Rx,{R1,R2,R3} 3,4,4 1,2,2 LDMIA Rx,{R1,R2,R3,R4} 3,4,4,5 1,2,2,3 LDMIA Rx,{R1,R2,R3,R4,R5} 3,4,4,5,5 1,2,2,3,4 LDMIA Rx,{R1,R2,R3,R4,R5,R6} 3,4,4,5,5,6 1,2,2,3,4,4 LDMIA Rx,{R1,R2,R3,R4,R5,R6,R7} 3,4,4,5,5,6,6 1,2,2,3,4,4,5 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-21 ID012310 Non-Confidential, Unrestricted Access...
Page 598: Table 16-19 Cycle Timing Behavior Of Load Multiples, Where The Pc Is In The Register List
The following that has an STM instruction takes five cycles to execute, because R6 has a register lock latency of four cycles: STMIA R0, {R1-R7} R6, R10, R11 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-22 ID012310 Non-Confidential, Unrestricted Access...
Page 599: 16.13 Rfe And Srs Instructions
Table 16-20 RFE and SRS instructions cycle timing behavior Cycle Example Instruction Memory Cycles Address double-word aligned RFEIA <Rn> SRSIA #<mode> Address not double-word aligned RFEIA <Rn> SRSIA #<mode> ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-23 ID012310 Non-Confidential, Unrestricted Access...
Page 600: 16.14 Synchronization Instructions
CLREX instructions have cycle timing behavior as for load instructions. Because they have no destination register, the result latency is not-applicable for such instructions. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-24 ID012310 Non-Confidential, Unrestricted Access...
Page 601: 16.15 Coprocessor Instructions
Table 16-22 Coprocessor Instructions cycle timing behavior Cycle Instruction Memory cycles Result latency MCRR MRRC As required LDC/LDCL As required STC/STCL ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-25 ID012310 Non-Confidential, Unrestricted Access...
Page 602: 16.16 Svc, Smc, Bkpt, Undefined, And Prefetch Aborted Instructions
SMC, BKPT, undefined, prefetch aborted instructions cycle timing behavior. Table 16-23 SVC, BKPT, undefined, prefetch aborted instructions cycle timing behavior Cycle Instruction BKPT Prefetch Abort Undefined Instruction ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-26 ID012310 Non-Confidential, Unrestricted Access...
Page 603: 16.17 No Operation
Cycle Timings and Interlock Behavior 16.17 No operation The no operation instruction, , takes two cycles. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 16-27 ID012310 Non-Confidential, Unrestricted Access...
Page 604: 16.18 Thumb Instructions
Cycle Timings and Interlock Behavior 16.18 Thumb instructions The cycle timing behavior for Thumb instructions follow the ARM equivalent instruction cycle timing behavior. Thumb BL instructions that are encoded as two Thumb instructions, can be dynamically predicted. The predictions occurs on the second part of the BL pair, consequently a correct prediction takes two cycles.
Page 605: Chapter 17 Ac Characteristics
This chapter gives the timing diagrams and timing parameters for the processor. This chapter contains the following sections: • Processor timing diagrams on page 17-2 • Processor timing parameters on page 17-3. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-1 ID012310 Non-Confidential, Unrestricted Access...
Page 606: Processor Timing Diagrams
Processor timing diagrams The AMBA AXI bus interface of the processor conforms to the AMBA Specification. See this document for the relevant timing diagrams. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-2 ID012310 Non-Confidential, Unrestricted Access...
Page 607: Processor Timing Parameters
Table 17-2 lists the AXI interface timing parameters. Table 17-2 AXI signals Name Minimum input delay Maximum input delay% ARREADYD Clock uncertainty ARREADYI Clock uncertainty ARREADYP Clock uncertainty ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-3 ID012310 Non-Confidential, Unrestricted Access...
Page 608 RRESPRW[1:0] Clock uncertainty RVALIDD Clock uncertainty RVALIDI Clock uncertainty RVALIDP Clock uncertainty RVALIDRW Clock uncertainty WREADYD Clock uncertainty WREADYP Clock uncertainty WREADYRW Clock uncertainty ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-4 ID012310 Non-Confidential, Unrestricted Access...
Page 609: Table 17-3 Coprocessor Signals
Minimum input delay Maximum input delay% INTSYNCEN Clock uncertainty IRQADDR[31:2] Clock uncertainty IRQADDRV Clock uncertainty IRQADDRVSYNCE Clock uncertainty nFIQ Clock uncertainty nIRQ Clock uncertainty ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-5 ID012310 Non-Confidential, Unrestricted Access...
Page 610: Table 17-6 Debug Interface Signals
Table 17-8 Static configuration signals Name Minimum input delay Maximum input delay% BIGENDINIT Clock uncertainty INITRAM Clock uncertainty UBITINIT Clock uncertainty VINITHI Clock uncertainty ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-6 ID012310 Non-Confidential, Unrestricted Access...
Page 611: Table 17-9 Trustzone Internal Signals
Table 17-9 lists the internal TrustZone signal port timing parameters. Table 17-9 TrustZone internal signals Name Minimum input delay Maximum input delay% CP15SDISABLE Clock uncertainty ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 17-7 ID012310 Non-Confidential, Unrestricted Access...
Page 612: Chapter 18 Introduction To The Vfp Coprocessor
• VFP11 treatment of branch instructions on page 18-15 • Writing optimal VFP11 code on page 18-16 • VFP11 revision information on page 18-17. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-1 ID012310 Non-Confidential, Unrestricted Access...
Page 613: About The Vfp11 Coprocessor
• low power consumption, small die size, and reduced kernel code. The VFP11 coprocessor is an ARM enhanced numeric coprocessor that provides operations that are compatible with the IEEE 754 standard. Designed for the ARM11 family of cores, the VFP11 coprocessor fully supports single-precision and double-precision add, subtract, multiply, divide, multiply and accumulate, and square root operations.
Page 614: Applications
• set-top boxes for digital audio and digital video, and three-dimensional user interfaces • automotive applications for engine management and power train computations. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-3 ID012310 Non-Confidential, Unrestricted Access...
Page 615: Coprocessor Interface
Access to the VFP11 coprocessor is controlled by the ARM11 Coprocessor Access Control Register. The coprocessor access rights must be configured correctly before any VFP11 instructions can be executed. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-4 ID012310 Non-Confidential, Unrestricted Access...
Page 616: Vfp11 Coprocessor Pipelines
18.4.1 FMAC pipeline Figure 18-1 on page 18-6 shows the structure of the FMAC pipeline. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-5 ID012310 Non-Confidential, Unrestricted Access...
Page 617: Figure 18-1 Fmac Pipeline
Convert float to signed integer. FTOUIZ Convert float to unsigned integer with forced round-towards-zero mode. FTOSIZ Convert float to signed integer with forced round-towards-zero mode. FCMP Compare. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-6 ID012310 Non-Confidential, Unrestricted Access...
Page 618 FMACS S0, S1, S2 FMULS TEMP, S1, S2 FADDS S0, S0, TEMP 18.4.2 DS pipeline Figure 18-2 on page 18-8 shows the structure of the DS pipeline. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-7 ID012310 Non-Confidential, Unrestricted Access...
Page 619: Figure 18-2 Ds Pipeline
ARM11 processor. Load data is written to the VFP11 coprocessor on a dedicated 64-bit load bus between the ARM11 processor and all coprocessors. Data is received by the VFP11 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-8 ID012310...
Page 620: Figure 18-3 Ls Pipeline
Move an ARM11 register value to the lower half of a VFP11 double-precision register. FMRDH Move the upper half of a double-precision value from a VFP11 double-precision register to an ARM11 register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-9 ID012310 Non-Confidential, Unrestricted Access...
Page 621 Move a VFP11 control register value to an ARM11 register. FMSTAT Move N, C, Z, and V flags from the VFP11 FPSCR to the ARM11 CPSR. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-10 ID012310 Non-Confidential, Unrestricted Access...
Page 622: Modes Of Operation
• passes control to the user trap handler and supplies any specified intermediate result for the exception if an enabled exception is detected. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-11 ID012310 Non-Confidential, Unrestricted Access...
Page 623 Operation, and Division by Zero exceptions. The underflow flag is modified for flush-to-zero mode. Each of these flags is set by an exceptional condition and can by cleared only by a write to the FPSCR register. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-12 ID012310 Non-Confidential, Unrestricted Access...
Page 624: Short Vector Instructions
See Chapter 21 VFP Instruction Execution for more information on execution of short vector instructions. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-13 ID012310 Non-Confidential, Unrestricted Access...
Page 625: Parallel Execution Of Instructions
The VFP11 coprocessor provides the ability to execute several floating-point operations in parallel, while the ARM11 processor is executing ARM instructions. While a short vector operation executes for a number of cycles in the VFP11 coprocessor, it appears to the ARM11 processor as a single-cycle instruction and is retired in the ARM11 processor before it completes execution in the VFP11 coprocessor.
Page 626: Vfp11 Treatment Of Branch Instructions
FCMP instruction followed by an FMSTAT instruction. For more information, see Compliance with the IEEE 754 standard on page 20-3 and Comparisons on page 20-5. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-15 ID012310...
Page 627: Writing Optimal Vfp11 Code
If fully compliant IEEE 754 standard comparisons are not required, avoid using FCMPE and FCMPEZ. Using an FMRS instruction with an ARM11 CMP or CMN can be faster for simple comparisons. See Comparisons on page 20-5. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-16 ID012310 Non-Confidential, Unrestricted Access...
Page 628: 18.10 Vfp11 Revision Information
• update to the FPSID register to reflect the fifth version. There are no other functional differences between the VFP11 fourth and fifth versions. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 18-17 ID012310 Non-Confidential, Unrestricted Access...
Page 629: Chapter 19 The Vfp Register File
Maintaining consistency in register precision on page 19-8 • Data transfer between memory and VFP11 registers on page 19-9 • Access to register banks in CDP operations on page 19-10. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-1 ID012310 Non-Confidential, Unrestricted Access...
Page 630: About The Register File
LEN and STRIDE fields in the FPSCR register specify the number of operations performed by short vector instructions and the increment scheme within the circular register banks. Section C5 of the ARM Architecture Reference Manual contains more information and examples. ARM DDI 0301H Copyright ©...
Page 631: Register File Internal Formats
However, to ensure compatibility with future VFP implementations, use FLDMX/FSTMX instructions when saving context and restoring VFP11 registers. See section C5 of the ARM Architecture Reference Manual for more information. It is the responsibility of the programmer to be aware of the data type in each register. The hardware does not perform any checking of the agreement between the data type in the source registers and the data type expected by the instruction.
Page 632: Figure 19-2 Double-Precision Data Format
The IEEE 754 standard defines the double-precision data format used in the VFP11 coprocessor. See the IEEE 754 standard for details about exponent bias, special formats, and numerical ranges. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-4 ID012310 Non-Confidential, Unrestricted Access...
Page 633: Decoding The Register File
M, N, and D bit corresponding to a double-precision access must be zero. Figure 19-3 shows the register file. See the ARM Architecture Reference Manual for instruction formats and the positions of these bits.
Page 634: Loading Operands From Arm11 Registers
Sm and S(m + 1). S(m + 1) = Rn MRRC instructions transfer 64-bit quantities from VFP11 registers to ARM11 registers as Table 19-4 on page 19-7 lists. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-6 ID012310 Non-Confidential, Unrestricted Access...
Page 635: Table 19-4 Vfp11 Mrrc Instructions
Rd = Sm Move from single-precision VFP11 registers Sm and S(m + 1) to ARM11 registers Rd and Rn. Rn = S(m + 1) ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-7 ID012310 Non-Confidential, Unrestricted Access...
Page 636: Maintaining Consistency In Register Precision
The hardware interprets the data in the format required by the instruction regardless of the latest store or write operation to the register. It is the task of the compiler or programmer to maintain consistency in register usage. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-8 ID012310 Non-Confidential, Unrestricted Access...
Page 637: Data Transfer Between Memory And Vfp11 Registers
19.6 Data transfer between memory and VFP11 registers The B bit in the CP15 c1 Control Register, see Section B2 of the ARM Architecture Reference Manual, determines whether access to stored memory is little-endian or big-endian. The ARM11 processor supports both little-endian and big-endian access formats in memory.
Page 638: Access To Register Banks In Cdp Operations
CDP instructions access the banks in a circular manner. Load and store multiple instructions do not access the registers in a circular manner but treat the register file as a linearly ordered structure. See ARM Architecture Reference Manual, Part C for more information on VFP addressing modes. Bank 0...
Page 639 ; 1st iteration FMACS S17, S1, S9 ; 2nd iteration FMACS S18, S2, S10 ; 3rd iteration FMACS S19, S3, S11 ; 4th and last iteration ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-11 ID012310 Non-Confidential, Unrestricted Access...
Page 640 ; scalar increment of S0 by S31 FMULS S24, S26, S1 ; vector (S26, S27) scaled by S1 and written to (S24, S25) FMULS S25, S27, S1 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-12 ID012310 Non-Confidential, Unrestricted Access...
Page 641: Table 19-7 Single-Precision Three-Operand Register Usage
Operation type b000 S = op S Nonzero S = op S Nonzero 4-15 V = op S Nonzero 4-15 4-15 V = op V ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 19-13 ID012310 Non-Confidential, Unrestricted Access...
Page 642: Chapter 20 Vfp Programmer's Model
• Compliance with the IEEE 754 standard on page 20-3 • ARMv5TE coprocessor extensions on page 20-8 • VFP11 system registers on page 20-12. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-1 ID012310 Non-Confidential, Unrestricted Access...
Page 643: About The Programmer's Model
The VFPv2 architecture adds the following features and enhancements to the VFPv1 architecture: • The ARM v5TE instruction set. This includes the MRRC and MCRR instructions to transfer 64-bit data between the ARM11 processor and the VFP11 coprocessor. These instructions enable the transfer of a double-precision register or two consecutively numbered single-precision registers to or from a pair of ARM11 registers.
Page 644: Compliance With The Ieee 754 Standard
• hardware and software components • software-based components and their availability. Also see Section C1 of the ARM Architecture Reference Manual for information about VFP architecture compliance with the IEEE 754 standard. 20.2.1 An IEEE 754 standard-compliant implementation The VFP11 hardware and support code together provide VFPv2 floating-point instruction implementations that are compliant with the IEEE 754 standard.
Page 645: Table 20-1 Default Nan Values
If IOE is not set, a default QNaN is written to the destination register. The rules for cases involving multiple NaN operands are in the ARM Architecture Reference Manual. Processing of input NaNs for ARM floating-point coprocessors and libraries is defined as follows: •...
Page 646: Table 20-2 Qnan And Snan Handling
See the ARM Architecture Reference Manual for mapping of IEEE 754 standard predicates to ARM conditions. The condition code flags used are chosen so that subsequent conditional execution of ARM instructions can test the predicates defined in the IEEE 754 standard.
Page 647 In the generation of Underflow exceptions, the after rounding form of tininess and the subnormalization loss form of loss of accuracy as the IEEE 754 standard describes are used. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-6 ID012310...
Page 648 UFC flag, FPSCR[3], is set. Support code is not involved. See Part C of the ARM Architecture Reference Manual for information on flush-to-zero mode. When the VFP11 coprocessor is not in flush-to-zero mode, any operation with a risk of producing a tiny result bounces to support code.
Page 649: Armv5Te Coprocessor Extensions
Specifies the source ARM11 register for the upper 32 bits of the operand. <Rn> Architecture version D variants only Exceptions None Operation if ConditionPassed(cond) then Dm[upper half] = Rn Dm[lower half] = Rd ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-8 ID012310 Non-Confidential, Unrestricted Access...
Page 650: Figure 20-2 Fmrrd Instruction Format
Arithmetic instructions using Rd and Rn treat the contents as an integer, whereas most VFP instructions treat the Dm value as a double-precision floating-point number. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-9 ID012310 Non-Confidential, Unrestricted Access...
Page 651: Figure 20-3 Fmsrr Instruction Format
S(m + 1) values as single-precision floating-point numbers. Invalid register lists If Sm is b1111 and M is 1, an encoding of S31, the instruction is Unpredictable. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-10 ID012310 Non-Confidential, Unrestricted Access...
Page 652: Figure 20-4 Fmrrs Instruction Format
If Sm is b1111 and M is 1, an encoding of S31, the instruction is Unpredictable. Use of R15 If R15 is specified for Rd or Rn, the results are Unpredictable. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-11 ID012310 Non-Confidential, Unrestricted Access...
Page 653: Vfp11 System Registers
Also, the FPEXC register contains additional bits to support exceptional conditions. These registers are designed to be used with the support code software available from ARM Limited. As a result, this document does not fully specify exception handling in all cases.
Page 654: Table 20-4 Accessing Vfp11 System Registers
FPSID is a read-only register that identifies the VFP11 coprocessor. Figure 20-5 shows the FPSID bit fields. 24 23 16 15 Part number Variant Revision Implementer Format Architecture Figure 20-5 Floating-Point System ID Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-13 ID012310 Non-Confidential, Unrestricted Access...
Page 655: Table 20-5 Fpsid Bit Fields
12 11 10 9 8 7 4 3 2 1 0 N Z C V Rmode Stride Figure 20-6 Floating-Point Status and Control Register ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-14 ID012310 Non-Confidential, Unrestricted Access...
Page 656: Table 20-6 Encoding Of The Floating-Point Status And Control Register
Should Be Zero Inexact cumulative exception flag Underflow cumulative exception flag Overflow cumulative exception flag Division by Zero cumulative exception flag Invalid Operation cumulative exception flag ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-15 ID012310 Non-Confidential, Unrestricted Access...
Page 657: Table 20-7 Vector Length And Stride Combinations
The EN bit, FPEXC[30], is the VFP enable bit. Clearing EN disables the VFP11 coprocessor. The VFP11 coprocessor clears the EN bit on reset. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-16 ID012310 Non-Confidential, Unrestricted Access...
Page 658: Table 20-8 Encoding Of The Floating-Point Exception Register
FPINST2 instruction valid flag. Set when FPINST2 contains a valid instruction. FP2V must be cleared by the exception handling routine. [27:11] Should Be Zero. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-17 ID012310 Non-Confidential, Unrestricted Access...
Page 659 The instruction in the FPINST2 register is in the same format as the issued instruction but is modified by forcing the condition code flags, FPINST2[31:28] to b1110, the AL, always, condition. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-18 ID012310 Non-Confidential, Unrestricted Access...
Page 660: Table 20-9 Media And Vfp Feature Register 0 Bit Functions
[31:28] Indicates the VFP hardware support level when user traps are disabled. , In ARM1176JZF-S processors when Flush-to-Zero and Default_NaN and Round-to-Nearest are all selected in FPSCR, the coprocessor does not require support code. Otherwise floating point support code is required.
Page 661: Table 20-10 Media And Vfp Feature Register 1 Bit Functions
Indicates support for media extension, load/store instructions. , no support in ARM1176JZF-S processors. The values in the Media and VFP Feature Register 1 are implementation defined. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 20-20 ID012310 Non-Confidential, Unrestricted Access...
Page 662: Chapter 21 Vfp Instruction Execution
Chapter 21 VFP Instruction Execution This chapter describes the VFP11 instruction pipeline and its relationship with the ARM processor instruction pipeline. It contains the following sections: • About instruction execution on page 21-2 • Serializing instructions on page 21-3 •...
Page 663: About Instruction Execution
The L/S, FMAC, and DS pipelines operate independently, enabling data transfer and CDP operations to execute in parallel. See Parallel execution on page 21-20. Execution timing on page 21-22 describes VFP11 instruction throughput and latency. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-2 ID012310 Non-Confidential, Unrestricted Access...
Page 664: Serializing Instructions
In general, an access to a VFP11 control or status register is a serializing instruction. The serializing instructions are FMRX and FMXR, including the FMSTAT instruction. Serializing instructions stall the VFP11 coprocessor in the Issue stage and the ARM processor in the Execute 2 stage until: •...
Page 665: Interrupting The Vfp11 Coprocessor
21.3 Interrupting the VFP11 coprocessor Instructions are issued to the VFP11 coprocessor directly from the ARM prefetch unit. The VFP11 coprocessor has no external interface beyond the ARM processor and cannot be separately interrupted by external sources. Any interrupt that causes a change of flow in the ARM11 processor is also reflected to the VFP11 coprocessor.
Page 666: Forwarding
FMULD is written to the register file. No forwarding is done from the FMULD to the store instruction. Example 21-3 Data not forwarded to store instruction FMULD D1, D2, D3 FSTD D1, [Rx] ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-5 ID012310 Non-Confidential, Unrestricted Access...
Page 667: Hazards
It is a hazard to the intended write-after-write operand access. • Resource hazard. See Resource hazards on page 21-17. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-6 ID012310 Non-Confidential, Unrestricted Access...
Page 668: Operation Of The Scoreboards
5 and above. When the vector length exceeds two double-precision iterations, the source scoreboard locks the source registers for iterations 3 and above. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-7 ID012310 Non-Confidential, Unrestricted Access...
Page 669: Table 21-1 Single-Precision Source Register Locking
In full-compliance mode, the source scoreboard locks S16-S20 and S24-S28 in the Issue stage of the instruction. In RunFast mode, the source scoreboard locks only the fifth iteration source registers, S20 and S28. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-8 ID012310 Non-Confidential, Unrestricted Access...
Page 670: Table 21-2 Single-Precision Source Register Clearing
In RunFast mode, the source scoreboard locks only the fifth iteration source registers, S20 and S28. It clears S20 and S28 in the second Execute 1 cycle of the instruction. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-9 ID012310...
Page 671: Table 21-3 Double-Precision Source Register Locking
• Instructions with one-cycle throughput on page 21-11 • Instructions with two-cycle throughput on page 21-11. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-10 ID012310 Non-Confidential, Unrestricted Access...
Page 672: Table 21-4 Double-Precision Source Register Clearing For One-Cycle Instructions
Source registers cleared in Execute 1 stage of each iteration Execute 1 cycle Full-compliance mode RunFast mode Iteration 1 registers Iteration 3 registers Iteration 2 registers Iteration 4 registers ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-11 ID012310 Non-Confidential, Unrestricted Access...
Page 673 D11 and D15, are locked. The source scoreboard clears D10 and D14 in the first Execute 1 cycle and clears D11 and D15 in the third Execute 1 cycle of the instruction. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-12 ID012310...
Page 674: Data Hazards In Full-Compliance Mode
VFP11 coprocessor. S15 is forwarded from the load in cycle 9 to the FADDS. Example 21-5 FLDM-FADDS RAW hazard FLDM [Rx], {S8-S15} FADDS S1, S2, S15 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-13 ID012310 Non-Confidential, Unrestricted Access...
Page 675: Table 21-7 Fldm-Fadds Raw Hazard
10 to the Issue stage of the FADDS. Example 21-7 FMULS-FADDS RAW hazard FMULS S4, S1, S0 FADDS S5, S4, S3 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-14 ID012310 Non-Confidential, Unrestricted Access...
Page 676: Table 21-9 Fmuls-Fadds Raw Hazard
Table 21-10 lists the VFP11 pipeline stages for the first iteration of Example 21-8. Table 21-10 Short vector FMULS-FLDMS WAR hazard Instruction cycle number Instruction FMULS FLDMS ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-15 ID012310 Non-Confidential, Unrestricted Access...
Page 677: Data Hazards In Runfast Mode
Table 21-11 shows that the VFP11 coprocessor does not stall the FLDMS operation. Table 21-11 Short vector FMULS-FLDMS WAR hazard in RunFast mode Instruction cycle number Instruction FMULS FLDMS ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-16 ID012310 Non-Confidential, Unrestricted Access...
Page 678: Resource Hazards
FLDM until the FLDM enters the final Execute cycle. The FADDS is stalled for one cycle until the FLDS begins execution. Example 21-10 FLDM-FLDS-FADDS resource hazard FLDM [R2], {S8-S10} FLDS [R4], S16 FADDS S2, S3, S4 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-17 ID012310 Non-Confidential, Unrestricted Access...
Page 679: Table 21-12 Fldm-Flds-Fadds Resource Hazard
Table 21-14 on page 21-19 lists, as E1. The first and shared Execute 1 cycle for each divide iteration is designated as E1’. Example 21-12 Short vector FDIVS-FADDS resource hazard FDIVS S8, S10, S12 FADDS S0, S0, S1 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-18 ID012310 Non-Confidential, Unrestricted Access...
Page 680: Table 21-14 Short Vector Fdivs-Fadds Resource Hazard
Table 21-14 lists the pipeline stages for Example 21-12 on page 21-18. Table 21-14 Short vector FDIVS-FADDS resource hazard Instruction cycle number … … FDIVS … … 1’ 1’ FADDS … W … ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-19 ID012310 Non-Confidential, Unrestricted Access...
Page 681: 21.10 Parallel Execution
STRIDE field contains b00, for a vector stride of one. Example 21-13 Parallel execution in all three pipelines FLDM [R4], {S4-S13} FDIVS S0, S1, S2 FADDS S16, S20, S24 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-20 ID012310 Non-Confidential, Unrestricted Access...
Page 682: Table 21-15 Parallel Execution In All Three Pipelines
E1’ is the first cycle in E1 and is in both FMAC and DS blocks. Subsequent E1 cycles represent the iteration cycles and occupy both E1 and E2 stages in the DS block. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-21 ID012310...
Page 683: 21.11 Execution Timing
FMXR and FMRX are serializing instructions. The latency depends on the register transferred and the current activity in the VFP11 coprocessor when the instruction is issued. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 21-22 ID012310...
Page 684: Chapter 22 Vfp Exception Handling
• Underflow exception on page 22-17 • Inexact exception on page 22-18 • Input exceptions on page 22-19 • Arithmetic exceptions on page 22-20. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-1 ID012310 Non-Confidential, Unrestricted Access...
Page 685: About Exception Processing
For descriptions of each of the exception flags and their bounce characteristics, see the sections Input Subnormal exception on page 22-12 to Arithmetic exceptions on page 22-20. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-2 ID012310...
Page 686: Bounced Instructions
Normally, the VFP11 hardware executes floating-point instructions completely in hardware. However, the VFP11 coprocessor can, under certain circumstances, refuse to accept a floating-point instruction, causing the ARM Undefined Instruction exception. This is known as bouncing the instruction. There are three reasons for bouncing an instruction: •...
Page 687 Overflow user trap handler. If the operation does not result in an overflow, it writes the computed result to the destination, sets the appropriate flags in the FPSCR, and returns to user code. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-4 ID012310 Non-Confidential, Unrestricted Access...
Page 688: Support Code
See Application Note 98, VFP Support Code for details of support code. Support code is provided with the RealView Compilation Tools, or for the ARM Developer Suite as an add-on downloadable from the ARM web site.
Page 689 If and when it returns, it causes the illegal instruction to be retried and the sequence of events that the paragraph above describes occurs. The following instruction types are architecturally Undefined. See ARM Architecture Reference Manual, Rev E, Part C: •...
Page 690 VFP Exception Handling • a short vector instruction with overlapping source and destination register addresses that are not exactly the same. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-7 ID012310 Non-Confidential, Unrestricted Access...
Page 691: Exception Processing
For short vector instructions, any iteration might be exceptional. If an exceptional condition is detected for a vector iteration, the vector iterations issued before the exceptional iteration are permitted to complete and retire. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-8 ID012310 Non-Confidential, Unrestricted Access...
Page 692: Table 22-1 Exceptional Short Vector Fmuld Followed By Load/Store Instructions
The VFP11 coprocessor is in the exceptional state. FP2V FPINST2 does not contain a valid instruction. VECITR 000 One iteration remains after the exceptional iteration. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-9 ID012310 Non-Confidential, Unrestricted Access...
Page 693: Table 22-2 Exceptional Short Vector Fadds With A Fadds In The Pretrigger Slot
Fm source is of the second exceptional iteration is S29. The FPINST2 register contains the instruction word for the second FADDS with the condition field changed to AL. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-10 ID012310 Non-Confidential, Unrestricted Access...
Page 694: Table 22-3 Exceptional Short Vector Faddd With An Fmacs Trigger Instruction
Fn source of the first exceptional iteration is D4. Fm/M 1100/0 Fm source of the first exceptional iteration is D12. FPINST2 contains invalid data. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-11 ID012310 Non-Confidential, Unrestricted Access...
Page 696: Invalid Operation Exception
An FMAC family operation with an infinity in the A operand and a potential product overflow when an infinity with the sign of the product would result in an invalid condition. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-13 ID012310...
Page 697: Table 22-5 Default Results For Invalid Conversion Inputs
A negative input to an unsigned conversion that does not round to a true zero in the conversion process sets the IOC flag, FPEXC[0]. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-14 ID012310 Non-Confidential, Unrestricted Access...
Page 698: Division By Zero Exception
Clearing the DZE bit disables Division by Zero exceptions. A correctly signed infinity is written to the destination register, and the DZC flag, FPSCR[1], is set. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-15 ID012310 Non-Confidential, Unrestricted Access...
Page 699: Overflow Exception
Round towards minus infinity Largest positive value for the destination size if positive overflow. Negative infinity if negative overflow. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-16 ID012310 Non-Confidential, Unrestricted Access...
Page 700: Underflow Exception
If the intermediate value was the minimum normal value before the underflow condition test is made, it is not flushed to zero. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-17 ID012310 Non-Confidential, Unrestricted Access...
Page 701: 22.10 Inexact Exception
If the IXE bit, FPSCR[12], is not set, the VFP11 coprocessor writes the result to the destination register and sets the IXC flag, FPSCR[4]. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-18 ID012310 Non-Confidential, Unrestricted Access...
Page 702: 22.11 Input Exceptions
When the IOE bit is clear, and the VFP11 coprocessor is not in default NaN mode, the instruction bounces to the support code. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-19 ID012310 Non-Confidential, Unrestricted Access...
Page 704: Table 22-8 Fadd Family Bounce Thresholds
DP underflow Bounce a. DP = double-precision. b. SP = single-precision. 22.12.2 FCMP, FCMPZ, FCMPE, and FCMPEZ Compare operations do not generate potential exceptions. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-21 ID012310 Non-Confidential, Unrestricted Access...
Page 705: Table 22-9 Fmul Family Bounce Thresholds
The bounce thresholds for the FADD family in Table 22-8 on page 22-21 and for the FMUL family in Table 22-9 incorporate this additional factor. Those ranges are used to detect potential exceptions for the FMAC family. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-22 ID012310 Non-Confidential, Unrestricted Access...
Page 706: Table 22-10 Fdiv Bounce Thresholds
DP underflow Bounce 0x000 a. DP = double-precision. b. SP = single-precision. 22.12.6 FSQRT It is not possible for FSQRT to overflow or underflow. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-23 ID012310 Non-Confidential, Unrestricted Access...
Page 707: Table 22-11 Fcvtsd Bounce Thresholds
These input values are bounced for unsigned conversions in all rounding modes. These input values are bounced for unsigned conversions in all rounding modes except round-towards-zero. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-24 ID012310 Non-Confidential, Unrestricted Access...
Page 708: Table 22-12 Single-Precision Float-To-Integer Bounce Thresholds And Stored Results
0xFF800000 0x00000000 0x80000000 a. SP = single-precision. b. A negative input value that rounds to a zero result returns zero and is not invalid. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-25 ID012310 Non-Confidential, Unrestricted Access...
Page 709: Table 22-13 Double-Precision Float-To-Integer Bounce Thresholds And Stored Results
0x00000000 00000000 none Valid Valid 0x00000000 0x00000000 –0 Invalid Valid 0x80000000 00000000 0x00000000 0x00000000 –23 Valid 0xC1CFFFFF FFFFFFFF –2 0xC0000001 Bounce U Valid 0xC0000000 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-26 ID012310 Non-Confidential, Unrestricted Access...
Page 710 Invalid Bounce all a. DP = double-precision. b. A negative input value that rounds to a zero result returns zero and is not invalid. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. 22-27 ID012310 Non-Confidential, Unrestricted Access...
Page 711: Appendix A Signal Descriptions
The output signals that Table A-1 on page A-2 to Table A-14 on page A-16 list are set to 0 on reset unless otherwise stated. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 712: Global Signals
Input Request for synchronous or asynchronous mode of DMA IEM Register Slice SYNCMODEACKI Output Acknowledge for synchronous or asynchronous mode of Instruction IEM Register Slice ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 713 Output Acknowledge for synchronous or asynchronous mode of Peripheral IEM Register Slice SYNCMODEACKD Output Acknowledge for synchronous or asynchronous mode of DMA IEM Register Slice ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 714: Static Configuration Signals
Instruction TCM Region Register on page 3-91. UBITINIT Input When HIGH indicates ARMv6 unaligned behavior. VINITHI Input When HIGH indicates High Vecs mode. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 715: Trustzone Internal Signals
CP15SDISABLE Input Disables write access to some system control processor registers SECMONBUS[24:0] Output Monitors the state of some of the key signals in the processor ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 716: Interrupt Signals, Including Vic Interface
Because this signal is level-sensitive, to generate an interrupt you must ensure it is held LOW until the processor sends a suitable interrupt response. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 717: Axi Interface Signals
Table A-6 on page A-8 gives more information about the instruction read port AXI ® implementation. See the AMBA AXI Protocol V1.0 Specification for details of the other signals on this port. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 718: Table A-6 Instruction Read Port Axi Signal Implementation
Table A-7 on page A-9 gives more information about the data port AXI implementation. See the AMBA ® AXI Protocol V1.0 Specification for details of the other signals on this port. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 719: Table A-7 Data Port Axi Signal Implementation
AWID[3:0], WID[3:0], BID[3:0], ARID[3:0], and RID[3:0] signals are not • implemented the write data bus is implemented as WDATAP[31:0], and therefore the write strobe • signal is implemented as WSTRBP[3:0] ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 720: Table A-8 Peripheral Port Axi Signal Implementation
AWID[3:0], WID[3:0], BID[3:0], ARID[3:0], and RID[3:0] signals are not • implemented the write data bus is implemented as WDATAD[63:0], and therefore the write strobe • signal is implemented as WSTRBD[7:0] ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-10 ID012310 Non-Confidential, Unrestricted Access...
Page 721: Table A-9 Dma Port Signals
ARSIDEBANDD[4:0] Output Read Indicates read accesses to shared and inner cacheable memory. AWSIDEBANDD[4:0] Output Write Indicates write accesses to shared and inner cacheable memory. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-11 ID012310 Non-Confidential, Unrestricted Access...
Page 722: Coprocessor Interface Signals
Asserted to indicate that the length information in CPALENGTH is not valid. Input CPALENGTHT [3:0] The tag accompanying the length signal in CPALENGTH. Input CPAPRESENT[11:0] Input Indicates the coprocessors that are present. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-12 ID012310 Non-Confidential, Unrestricted Access...
Page 723 The store data passing from the coprocessor to the core. CPASTDATAT [3:0] The tag accompanying the store data in CPASTDATA. Input CPASTDATAV Input Indicates that the store data to the core is valid. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-13 ID012310 Non-Confidential, Unrestricted Access...
Page 724: Debug Interface Signals, Including Jtag
DBGNOPWRDWN Output Debugger has requested core is not powered down. SPIDEN Input Secure Privileged Invasive Debug Enable. SPNIDEN Input Secure Privileged Non-Invasive Debug Enable. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-14 ID012310 Non-Confidential, Unrestricted Access...
Page 725: Etm Interface Signals
Coprocessor write data. ETMCPWRITE Output Coprocessor write control. EVNTBUS[19:0] Output System metrics event bus. WFIPENDING Output Indicates a Pending Wait For Interrupt. Handshakes with nETMWFIREADY. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-15 ID012310 Non-Confidential, Unrestricted Access...
Page 726: Test Signals
Request for an interrupt nVALFIQ Output Request for a fast interrupt nVALRESET Output Request for a reset VALEDBGRQ Output Request for an external debug request ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. A-16 ID012310 Non-Confidential, Unrestricted Access...
Page 727: Appendix B Summary Of Arm1136Jf-S And Arm1176Jzf-S Processor Differences
Appendix B Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences This appendix describes the main differences between the ARM1136JF-S and ARM1176JZF-S processors. It contains these sections: • About the differences between the ARM1136JF-S and ARM1176JZF-S processors on page B-2 • Summary of differences on page B-3.
Page 728: About The Differences Between The Arm1136Jf-S And Arm1176Jzf-S Processors
Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences About the differences between the ARM1136JF-S and ARM1176JZF-S processors The ARM11 family of high performance processors implements the ARMv6 architecture and includes the ARM1136JF-S and ARM1176JZF-S processors. These have: • an integer core •...
Page 729: Summary Of Differences
The ARM1176JZF-S processor fully implements the TrustZone architecture for OS security enhancements. This leads to numerous differences between ARM1136JF-S and ARM1176JZF-S processors in the core and the Level 1 Memory System, see also Debug on page B-10. The ARM1176JZF-S processor embodies, for TrustZone: •...
Page 730: Figure
CP15 register 15. By moving one entry in the ARM1176JZF-S processor TEX CB encoding table, with an alias for compatibility, TEX[2:1] is freed for use as two OS managed page table bits. Because binary compatibility is important with existing ARMv6 ports of OSs, this change consists of a separate mode of operation of the MMU.
Page 731 SmartCache feature for the Tightly-Coupled Memories. As a consequence, the TCMs in ARM1176JZF-S processors always behave as local RAMs and the SC bit, bit [1], of each TCM Region Register is Read As Zero and Ignored on writes. The SmartCache dedicated valid and dirty RAMs are not implemented in the ARM1176JZF-S processor.
Page 732: Table B-1 Tcm For Arm1176Jzf-S Processors
• 64KB. The ARM1176JZF-S processor implements zero, one or two Tightly Coupled Memories on each side. For each side, the two TCMs are physically located within one RAM. Table B-1 lists the possible configurations for ARM1176JZF-S Tightly-Coupled Memories for each side:...
Page 733 This new IFAR is updated on prefetch aborts and contains the faulty instruction address. Note In Jazelle state, the IFAR is not as accurate as in ARM and Thumb states. In Jazelle state the IFAR does not contain the address of the faulty bytecode but only the address of the word or double-word that includes the faulty bytecode.
Page 734: Table B-2 Cp15 C15 Features Common To Arm1136Jf-S And Arm1176Jzf-S Processors
Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences Table B-2 lists the CP15 c15 registers and operations common to both ARM1176JZF-S and ARM1136JF-S processors. Table B-2 CP15 c15 features common to ARM1136JF-S and ARM1176JZF-S processors Opcode_1 Opcode_2 Register Function Peripheral Memory Remap...
Page 735: Table B-3 Cp15 C15 Only Found In Arm1136Jf-S Processors
Main TLB Valid Cache Debug Control TLB Debug Control a. In the ARM1136JF-S processor is possible to read and write all TLB entries. In ARM1176JZF-S processor you can only read or write the lockdown entries. B.2.12 DMA The ARM1176JZF-S processor transfers all data as part of the DMA transfer from TCM to external memory.
Page 736 ETM11 macrocell supports both the ARM1136JF-S and ARM1176JZF-S processors. System metrics In Debug state the system metrics counters are disabled in the ARM1176JZF-S processor. B.2.14 Level two interface The external interfaces of the two processors are different to this extent: •...
Page 737 It has one 32-bit AXI Peripheral interface. B.2.15 Memory BIST MBISTWE from the ARM1136JF-S processor is extended to 8 bits, MBISTWE[7:0], in ARM1176JZF-S processors to enable control of individual write enables for bit and byte write RAMs. ARM DDI 0301H Copyright ©...
Page 738: Table C-1 Differences Between Issue G And Issue H
Synchronization of the VIC port signals on page 12-4 Table A-4 on page A-6 Improve description of DBGEN signal. Table 13-22 on page 13-33 All revisions External signals on page 13-52 ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 739 Deselect DTR in debug sequence. Writing memory as words on page 14-37 All revisions Correct description of nETMWFIREADY signal. Table A-13 on page A-15 All revisions ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. ID012310 Non-Confidential, Unrestricted Access...
Page 740 See also Data Abort, External Abort and Prefetch Abort. Abort model An abort model is the defined behavior of an ARM processor in response to a Data Abort exception. Different abort models behave differently with regard to load and store instructions that specify base register write-back.
Page 741 A family of protocol specifications that describe a strategy for the interconnect. AMBA is the ARM open standard for on-chip buses. It is an on-chip bus specification that details a strategy for the interconnection and management of functional blocks that make up a System-on-Chip (SoC).
Page 742 Any VFPv2 Coprocessor Data Processing (CDP) instruction except FCPY, FABS, and FNEG. See also CDP instruction. ARM instruction A word that specifies an operation for an ARM processor to perform. ARM instructions must be word-aligned. ARM state A processor that is executing ARM (32-bit) word-aligned instructions is operating in ARM state.
Page 743 1. The letter x in the signal name denotes an AXI channel as follows: Write address channel. Write data channel. Write response channel. Read address channel. Read data channel. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. Glossary-4 ID012310 Non-Confidential, Unrestricted Access...
Page 744 Memory in which: - a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at that address ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. Glossary-5 ID012310 Non-Confidential, Unrestricted Access...
Page 745 The VFP coprocessor bounces an instruction when it fails to signal the acceptance of a valid VFP instruction to the ARM processor. This action initiates Undefined instruction processing by the ARM processor. The VFP support code is called to complete the instruction that was found to be exceptional or unsupported by the VFP coprocessor.
Page 746 The ARM architecture supports byte-invariant systems in ARMv6 and later versions. When byte-invariant support is selected, unaligned halfword and word memory accesses are also supported.
Page 747 Otherwise, the instruction does nothing. Context The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the Physical Address range that it can access in memory and the associated memory access permissions.
Page 748 JTAG boundary-scan architecture. The mandatory terminals are DBGTDI, DBGTDO, DBGTMS, and TCK. The optional terminal is TRST. This signal is mandatory in ARM cores because it is used to reset the debug logic. Default NaN mode A mode in which all operations that result in a NaN return the default NaN, regardless of the cause of the NaN result.
Page 749 A data item having a memory address that is divisible by eight. EmbeddedICE logic An on-chip logic block that provides TAP-based debug support for ARM processor cores. It is accessed through the TAP controller on the ARM core using the JTAG interface.
Page 750 In ARM processors, a fast context switch is caused by the selection of a non-zero PID value to switch the context to that of the next process. A fast context switch causes each Virtual Address for a memory access, generated by the ARM processor, to produce a Modified Virtual Address which is sent to the rest of the memory system to be used in place of a normal Virtual Address.
Page 751: Figure
Infinity In the IEEE 754 standard format to represent infinity, the exponent is the maximum for the precision and the fraction is all zeros. ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. Glossary-12 ID012310 Non-Confidential, Unrestricted Access...
Page 752: Figure
For example, after a cache flush all lines are invalid. Jazelle architecture The ARM Jazelle architecture extends the Thumb and ARM operating states by adding a Jazelle state to the processor. Instruction set support for entering and exiting Java applications, real-time interrupt handling, and debug support for mixed Java/ARM applications is present.
Page 753 See Memory Management Unit. Modified Virtual Address (MVA) A Virtual Address produced by the ARM processor can be changed by the current Process ID to provide a Modified Virtual Address (MVA) for the MMUs and caches. See also Fast Context Switch Extension.
Page 754 See also Fast Context Switch Extension. Read Reads are defined as memory operations that have the semantics of a load. That is, the ARM instructions LDM, LDRD, LDC, LDR, LDRT, LDRSH, LDRH, LDRSB, LDRB, LDRBT, LDREX, RFE, STREX, SWP, and SWPB, and the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.
Page 755 Processors can contain several shift registers to enable you to access selected parts of the device. SCREG The currently selected scan chain number in an ARM TAP controller. See Cache set. Set-associative cache In a set-associative cache, lines can only be placed in the cache in locations that correspond to the modulo division of the memory address by the number of sets.
Page 756 The collection of four mandatory and one optional terminals that form the input/output and control interface to a JTAG boundary-scan architecture. The mandatory terminals are TDI, TDO, TMS, and TCK. The optional terminal is TRST. This signal is mandatory in ARM cores because it is used to reset the debug logic.
Page 757 See also Bounce, Potentially exceptional instruction, and Exceptional state. Undefined Indicates an instruction that generates an Undefined instruction trap. See the ARM Architecture Reference Manual for more details on ARM exceptions. See Unpredictable.
Page 758 See also Byte-invariant. Write Writes are defined as operations that have the semantics of a store. That is, the ARM instructions SRS, STM, STRD, STC, STRT, STRH, STRB, STRBT, STREX, SWP, and SWPB, and the Thumb instructions STM, STR, STRH, STRB, and PUSH. Java instructions that are accelerated by hardware can cause a number of writes to occur, according to the state of the Java stack and the implementation of the Java hardware acceleration.
Page 759 Byte Cache way Cache set Cache line Word number Line number Cache tag RAM Cache data RAM Read data (way number) (way that corresponds) ARM DDI 0301H Copyright © 2004-2009 ARM Limited. All rights reserved. Glossary-20 ID012310 Non-Confidential, Unrestricted Access...

ARM ARM1176JZF-S Technical Reference Manual

Preface

Chapter 1 Introduction

Chapter 2 Programmer's Model

Chapter 3 System Control Coprocessor

Quick Links

Need help?

Questions and answers

Related Manuals for ARM ARM1176JZF-S

Summary of Contents for ARM ARM1176JZF-S