Operation Of Unaligned Accesses; Table 4-2 Memory Access Types - ARM ARM1176JZF-S Technical Reference Manual

4.4

Operation of unaligned accesses

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This section describes alignment faults and operation of non-faulting accesses of the processor.
Table 4-2 lists the memory access types.
The mechanism for the support of unaligned loads or stores is that if either the Base register or
the index offset of the address is misaligned, then the processor takes two cycles to issue the
instruction. If the resulting address is misaligned, then the instruction performs multiple
memory accesses in ascending order of address.
There is no support for misaligned accesses being atomic, and misaligned accesses to Device
memory might result in Unpredictable behavior.
Table 4-3 on page 4-14 lists details of when an alignment fault must occur for an access and of
when the behavior of an access is architecturally Unpredictable. When an access does not
generate an alignment fault, and is not Unpredictable, details of the precise memory locations
that are accessed are also given in the table.
The access type descriptions used in Table 4-3 on page 4-14 are determined from the load/store
instruction that Table 4-2 lists.
The following terminology is used to describe the memory locations accessed:
Byte[X] This means the byte whose address is X in the current endianness model. The
correspondence between the endianness models is that Byte[A] in the LE
endianness model, Byte[A] in the BE-8 endianness model, and Byte[A EOR 3] in
the BE-32 endianness model are the same actual byte of memory.
Halfword[X] This means the halfword consisting of the bytes whose addresses are X and X+1
in the current endianness model, combined to form a halfword in little-endian
order in the LE endianness model or in big-endian order in the BE-8 or BE-32
endianness model.
Word[X] This means the word consisting of the bytes whose addresses are X, X+1, X+2,
and X+3 in the current endianness model, combined to form a word in
little-endian order in the LE endianness model or in big-endian order in the BE-8
or BE-32 endianness model.
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Unaligned and Mixed-endian Data Access Support
Access type ARM instructions
Byte LDRB, LDRBT, STRB, STRBT
BSync SWPB, LDREXB, STREXB
Halfword LDRH, LDRSH, STRH
HWSync LDREXH, STREXH
WLoad LDR, LDRT, SWP, load access if U is set to 0
WStore STR, STRT, SWP, store access if U is set to 0
WSync LDREX, STREX, SWP, either access if U is set to 1
Two-word LDRD, STRD
Multi-word LDC, LDM, RFE, SRS, STC, STM
DWSync LDREXD, STREXD

Table 4-2 Memory access types

4-13