Table 3-25 Results Of Access To The Memory Model Feature Register 2; Table 3-26 Memory Model Feature Register 3 Bit Functions; Figure 3-20 Memory Model Feature Register 3 Format - ARM ARM1176JZF-S Technical Reference Manual

ARM DDI 0301H
ID012310
Table 3-25 lists the results of attempted access for each mode.

Table 3-25 Results of access to the Memory Model Feature Register 2

Secure Privileged
Read Write
Data Undefined exception
To use the Memory Model Feature Register 2 read CP15 with:
• Opcode_1 set to 0
• CRn set to c0
• CRm set to c1
• Opcode_2 set to 6.
For example:
MRC p15, 0, <Rd>, c0, c1, 6 ;Read Memory Model Feature Register 2.
c0, Memory Model Feature Register 3
The purpose of the Memory Model Feature Register 3 is to provide information about the
memory model, memory management, cache support, and TLB operations of the processor.
The Memory Model Feature Register 3 is:
• in CP15 c0
• a 32-bit read-only register common to the Secure and Non-secure worlds
• accessible in privileged modes only.
Figure 3-20 shows the bit arrangement for Memory Model Feature Register 3.
31 28 27 24 23
Reserved Reserved
Table 3-26 lists how the bit values correspond with the Memory Model Feature Register 3
functions.
Bits Field name
[31:8] -
[7:4] -
[3:0] -
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
Non-secure Privileged
Read Write
Data Undefined exception
20 19 16 15
Reserved Reserved Reserved

Figure 3-20 Memory Model Feature Register 3 format

Table 3-26 Memory Model Feature Register 3 bit functions

Function
Reserved. RAZ.
Support for hierarchical cache maintenance by MVA, all architectures
, no support in ARM1176JZF-S processors.
0x0
Support for hierarchical cache maintenance by Set/Way, all architectures.
0x0 , no support in ARM1176JZF-S processors.
System Control Coprocessor
User
Undefined exception
12 11 8 7 4 3
Reserved -
0
-
3-35