Figure 6-7 Armv6 First-Level Descriptor Formats With Subpages Disabled - ARM ARM1176JZF-S Technical Reference Manual

6.11.2 ARMv6 page table translation subpage AP bits disabled
Translation fault
Coarse page table
Section (1MB)
Supersection
(16MB)
Translation fault
ARM DDI 0301H
ID012310
When the CP15 Control Register c1 Bit 23 is set to 1 in the corresponding world, the subpage
AP bits are disabled and the page tables have support for ARMv6 MMU features. Four new page
table bits are added to support these features:
• The Not-Global (nG) bit, determines if the translation is marked as global (0), or
process-specific (1) in the TLB. For process-specific translations the translation is
inserted into the TLB using the current ASID, from the ContextID Register, CP15 c13.
• The Shared (S) bit, determines if the translation is for Non-Shared (0), or Shared (1)
memory. This only applies to Normal memory regions. Device memory can be Shared or
Non-Shared as determined by the TEX bits and the C and B bits.
• The Execute-Never (XN) bit, determines if the region is Executable (0) or Not-executable
(1).
• Three access permission bits. The access permissions extension (APX) bit, provides an
extra access permission bit.
All ARMv6 page table mappings support the TEX field.
ARMv6 page table format
With the sub-pages enabled or not, all first level descriptors have been enhanced with the
addition of the NS Attribute bit to enable the support of TrustZone.
Figure 6-7 shows the format of an ARMv6 first-level descriptor when subpages are disabled.
31 24
Coarse page table base address
Section base address Section base address
Supersection base
address
Reserved

Figure 6-7 ARMv6 first-level descriptor formats with subpages disabled

If the P bit is supported and set for the memory region, it indicates to the system memory
controller that this memory region has ECC enabled. ARM1176JZF-S processors do not support
the P bit. In addition to the invalid translation, bits [1:0] = b00, translations for the reserved
entry, bits [1:0] = b11, result in a translation fault.
As shown in Figure 6-7, bits [1:0] of a level 1 page table entry determine the type of the entry:
Bits [1:0] == b00
Translation fault.
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23 20 19 18 17 16 15 14
Ignored
A
N N n
0 S P
S S G
X
A
N n
SBZ 1 S P
S G
X
Memory Management Unit
12 11 10 9 8 5 4 3 2 1 0
P Domain
TEX AP AP P P Domain Domain
TEX AP P Ignored
0 0
S S
N
B B 0 1
S
Z Z
X X
C B 1 C B 1 0 0
N N
X
C B 1 0
N
1 1
6-39