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22.4.4
Examples of exception detection for vector instructions
Instruction
FMULD D8, D12, D8
FLDD D0, [R5]
FSTMS R3, {S2-S9}
FLDS S8, [R9]
ARM DDI 0301H
ID012310
When a short vector iteration is found to be potentially exceptional, the following operations
occur:
1.
The EX flag, FPEXC[31], is set.
2.
The source and destination register addresses are modified in the instruction word to point
to the source and destination registers of the potentially exceptional iteration.
3.
The FPINST register is loaded with the operation instruction word.
4.
The VECITR field, FPEXC[10:8], is written with the number of iterations remaining after
the potentially exceptional iteration.
5.
The exceptional condition flags are set in the FPEXC.
In Example 22-1, the FMULD instruction is a short vector operation with b011 in the LEN field
for a length of four iterations and b00 in the STRIDE field for a vector stride of one. A potential
Underflow exception is detected on the third iteration.
Example 22-1 Exceptional short vector FMULD followed by load/store instructions
FMULD D8, D12, D8
FLDD D0, [R5]
FSTMS R3, {S2-S9}
FLDS S8, [R9]
A double-precision multiply requires two cycles in the Execute 2 stage. The exception on the
third iteration is detected in cycle 8. Before the FMULD exception is detected, the FLDD enters
the Decode stage in cycle 2, and the FSTMS enters the Decode stage in cycle 3. The FLDD and
the FSTMS complete execution and retire. The FLDS stalls in the Decode stage because of a
resource conflict with the FSTMS and is the trigger instruction. It is bounced in cycle 9 and can
be retried after exception processing. FPINST2 is invalid, and the FP2V flag, FPEXC[28], is not
set.
Table 22-1 lists the pipeline stages for Example 22-1.
Table 22-1 Exceptional short vector FMULD followed by load/store instructions
Instruction cycle number
1
2
3
4
D
I
E1
E2
-
D
I
E
-
-
D
I
-
-
-
D
After exception processing begins, the FPEXC register fields contain the following:
EX
1
The VFP11 coprocessor is in the exceptional state.
EN
1
FP2V
0
FPINST2 does not contain a valid instruction.
VECITR
000 One iteration remains after the exceptional iteration.
INV
0
Copyright © 2004-2009 ARM Limited. All rights reserved.
Non-Confidential, Unrestricted Access
; Short vector double-precision multiply of length 4
; Load of 1 double-precision register
; Store multiple of 8 single-precision registers
; Load of 1 single-precision register
5
6
7
8
9
E1
E2
E1
E2
-
M1
M2
W
-
-
E
M1
M2
W
W
D
D
D
I
*
VFP Exception Handling
10
11
12
13
14
-
-
-
-
-
-
-
-
-
-
W
W
-
-
-
-
-
-
-
-
15
16
-
-
-
-
-
-
-
-
22-9
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