Table 11-2 Coprocessor Control Signals; Figure - ARM ARM1176JZF-S Technical Reference Manual

11.2.2 Coprocessor control
Signal
CLKIN
nRESETIN
ACPNUM[3:0]
ACPENABLE
ACPPRIV
11.2.3 Pipeline synchronization
ARM DDI 0301H
ID012310
Other instructions, for example MCR and MRC, transfer data between core and coprocessor
registers. The CDP instruction controls the execution of a specified operation on data already
held within the coprocessor, writing the result back into a coprocessor register, or changing the
state of the coprocessor in some other way. Opcode fields within the CDP instruction determine
the operation that is to be carried out.
The core pipeline handles both core and coprocessor instructions. The coprocessor, on the other
hand, only deals with coprocessor instructions, so the coprocessor pipeline is likely to be empty
for most of the time.
The coprocessor communicates with the core using several signals. Most of these signals control
the synchronizing queues that connect the coprocessor pipeline to the core pipeline. Table 11-2
lists the signals used for general coprocessor control.
Description
This is the clock signal from the core.
This is the reset signal from the core.
This is the fixed number assigned to the coprocessor, and is in the range 0-13. Coprocessor numbers
10, 11, 14, and 15 are reserved for system control coprocessors.
When set, enables the coprocessor to respond to signals from the core.
When asserted, indicates that the core is in privileged mode. This might affect the execution of certain
coprocessor instructions.
Figure 11-1 on page 11-5 shows an outline of the core and coprocessor pipelines and the
synchronizing queues that communicate between them. Each queue is implemented as a very
short First In First Out (FIFO) buffer.
No explicit flow control is required for the queues, because the pipeline lengths between the
queues limits the number of items any queue can hold at any time. The geometry used means
that only three slots are required in each queue.
The only status information required is a flag to indicate when the queue is empty. This is
monitored by the receiving end of the queue, and determines if the associated pipeline stage can
move on. Any information that the queue carries can also be read and acted on at the same time.
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Coprocessor Interface

Table 11-2 Coprocessor control signals

11-4