Figure 6-10 Creating A First-Level Descriptor Address - ARM ARM1176JZF-S Technical Reference Manual

31
31
Translation base
ARM DDI 0301H
ID012310
The OS can maintain a different pagetable for each process, and update TTRB0 on a context
switch. Using a truncated pagetable means that much less space is required to store the
individual process page tables. Different processes can have different size pagetables, that is,
different values of N, by updating the TTBCR during the context switch.
It is not required that the OS pagetables that TTBR1 points to are updated on a context switch.
Figure 6-10 shows how to create a first level descriptor address.
The PD0 and PD1 bits in TTBCR can be used to prevent pagetable walks from either TTBR. In
particular, disabling walks from TTBR1 and setting TTBR0 to the address of a truncated
translation table can minimize the overhead otherwise incurred in unused translation table
entries.
Translation table base 0
14-N 13-N
Translation base
32-N
First-level table index
14-N 13-N
Table index
31
31
First-level descriptor address
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3 2 1 0
P S C
Modified virtual address
20 19
2 1 0
0 0
Translation table base 1
14 13
Translation base
31
14 13
Translation base
Translation table base control:
If (N > 0 && MVA[31:32-N] != 0)
else
0 1
Where N is the value of the Translation
Table Base Control Register c2

Figure 6-10 Creating a first-level descriptor address

Memory Management Unit
0
3 2 1 0
P S C
Modified virtual address
20 19
First-level table index
2 1 0
Table index 0 0
{TTBR1[31:14], MVA[31:20], 00}
{TTBR0[31:14-N], MVA[31-N:20], 00}
0
6-44