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ARM ETB11 Embedded Trace Buffer Manuals
Manuals and User Guides for ARM ETB11 Embedded Trace Buffer. We have
1
ARM ETB11 Embedded Trace Buffer manual available for free PDF download: Technical Reference Manual
ARM ETB11 Technical Reference Manual (80 pages)
Brand:
ARM
| Category:
Computer Hardware
| Size: 0 MB
Table of Contents
Table of Contents
3
Preface
10
About this Document
10
Key to Timing Diagram Conventions
12
Feedback
14
Chapter 1 Introduction
16
About the Embedded Trace Buffer
16
Figure 1-1 System-On-Chip Debug Implementation
16
ETM Versions and Variants
19
Table 1-1 ETM Major Architecture Versions
19
Silicon Revision
20
Functional Information
22
Figure 2-1 ETB11 Module Block Diagram
23
Operation
24
Control Logic
26
Figure 2-2 Trace Capture Operation
26
Figure 2-3 Trace Read Operation
27
Data Formatter
28
Trigger Delay Counter
29
Address Generation
30
BIST Interface
31
Figure 2-4 BIST Interface Block Diagram
31
TAP Controller
32
Table 2-1 Supported Public Instructions
33
Trace RAM Interface
35
Table 2-2 Trace RAM Interface Signals
35
Figure 2-5 Read Access from Trace RAM Timing Diagram
36
Figure 2-6 Write Access to Trace RAM Timing Diagram
36
Clocks, and Resets
37
Figure 2-7 Example Synchronizer
37
AHB Transfers
39
Figure 2-8 Synchronization Logic between HCLK and CLK Domains
40
Figure 2-9 Software Read Cycle with Asynchronous CLK and HCLK
41
Figure 2-10 Software Read Cycle with Synchronous CLK and HCLK
42
Figure 2-11 Software Write Cycle with Asynchronous CLK and HCLK
44
Figure 2-12 Software Write Cycle with Synchronous CLK and HCLK
45
About the Programmer's Model
48
Table 3-1 Register Map
48
Register Descriptions
50
Table 3-2 Identification Register Description
50
Table 3-3 RAM Depth Register Bit Allocations
51
Table 3-4 RAM Width Register Bit Allocations
51
RAM Depth Register, R1
51
RAM Width Register, R2
51
Table 3-5 Status Register Bit Allocations
52
Status Register, R3
52
Table 3-6 RAM Data Register Bit Allocations
53
Table 3-7 RAM Read Pointer Register Bit Allocations
53
RAM Data Register, R4
53
RAM Read Pointer Register, R5
53
Table 3-8 RAM Write Pointer Register Bit Allocations
54
RAM Write Pointer Register, R6
54
Table 3-9 Trigger Counter Register Bit Allocations
55
Trigger Counter Register, R7
55
Table 3-10 Control Register Bit Allocations
56
Control Register, R8
56
Software Access to the ETB11 Using the AHB Interface
57
Table 3-11 Registers that Require Software Access
57
Chapter 4 Timing Requirements
60
AHB Interface
60
Table 4-1 AHB Interface Timing Requirements
60
Figure 4-1 AHB Interface Signals
60
CLK Domain
62
Table 4-2 CLK Domain Timing Requirements
62
Figure 4-2 CLK Domain Signals
62
IEEE1149.1 Interface
64
Table 4-3 IEEE1149.1 Interface Timing Requirements
64
Figure 4-3 IEEE1149.1 Interface Signals
64
Appendix A Signal Descriptions
65
Signal Properties and Requirements
66
Signal Descriptions
67
Table A-1 Signal Descriptions
67
ASIC Connections
72
Table B-1 ETB11 Connection Guide
72
Connecting to ETM11RV
73
Table B-2 ETB11 to Generic Trace Port Interface Connections
73
Connecting the ETB11 in a 64-Bit AHB System
74
Glossary
75
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