Table 8-43 Half-Line Write-Back; Table 8-44 Full-Line Write-Back - ARM ARM1176JZF-S Technical Reference Manual

8.5.20 Half-line Write-Back
Write address
[4:0]
-
0x00 0x07
-
0x08 0x0F
-
0x10 0x17
-
0x18 0x1F
8.5.21 Full-line Write-Back
ARM DDI 0301H
ID012310
Table 8-43 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for half-line Write-Backs over the Data Read/Write Interface.
Description
Evicted cache line valid
and lower half dirty
Evicted cache line valid
and upper half dirty
Evicted cache line valid
and lower half dirty
Evicted cache line valid
and upper half dirty
Evicted cache line valid
and lower half dirty
Evicted cache line valid
and upper half dirty
Evicted cache line valid
and lower half dirty
Evicted cache line valid
and upper half dirty
Table 8-44 shows the values of AWADDRRW, AWBURSTRW, AWSIZERW, and
AWLENRW for full-line Write-Backs, evicted cache line valid and both halves dirty, over the
Data Read/Write Interface.
Write address [4:0]
-
0x00 0x07
-
0x08 0x0F
-
0x10 0x17
-
0x18 0x1F
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AWADDRR AWBURSTR
W W
Incr
0x00
Incr
0x10
Wrap
0x08
Incr
0x10
Incr
0x00
Incr
0x10
Incr
0x00
Wrap
0x18
AWADDRR AWBURSTR
W W
Incr
0x00
Wrap
0x08
Wrap
0x10
Wrap
0x18
Level Two Interface

Table 8-43 Half-line Write-Back

AWSIZERW AWLENRW
64-bit 2 data transfers
64-bit 2 data transfers
64-bit 2 data transfers
64-bit 2 data transfers
64-bit 2 data transfers
64-bit 2 data transfers
64-bit 2 data transfers
64-bit 2 data transfers

Table 8-44 Full-line Write-Back

AWSIZERW AWLENRW
64-bit 4 data transfers
64-bit 4 data transfers
64-bit 4 data transfers
64-bit 4 data transfers
8-26