ARM ARM1176JZF-S Technical Reference Manual page 484

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Bits
Core view
[8]
R
[7]
R
[6]
R
ARM DDI 0301H
ID012310
Table 13-4 Debug Status and Control Register bit field definitions (continued)
External
Reset
Description
view
value
RC
0
Sticky Undefined flag:
0 = No Undefined exception trap occurred in Debug state since the last
time this bit was cleared.
1 = An undefined exception occurred while in Debug state since the
last time this bit was cleared.
This bit is cleared on reads of a DBGTAP debugger to the DSCR. The
Sticky Undefined bit does not prevent additional instructions from
being issued.
The Sticky Undefined bit is not set by Undefined exceptions occurring
when not in Debug state.
RC
0
Sticky imprecise Data Aborts flag:
0 = No imprecise Data Aborts occurred since the last time this bit was
cleared
1 = An imprecise Data Abort has occurred since the last time this bit
was cleared.
It is cleared on reads of a DBGTAP debugger to the DSCR.
The sticky imprecise data abort bit is only set by imprecise data aborts
occurring when in Debug state.
In previous versions of the debug architecture, the sticky imprecise
data abort was set when the processor took an imprecise data abort. In
version 6.1, it is set when an imprecise data abort is detected.
RC
0
Sticky precise Data Abort flag:
0 = No precise Data Abort occurred since the last time this bit was
cleared
1 = A precise Data Abort has occurred since the last time this bit was
cleared.
This flag is meant to detect Data Aborts generated by instructions
issued to the processor using the Debug Test Access Port. Therefore,
if the DSCR[13] execute ARM instruction enable bit is a 0, the value
of the sticky precise Data Abort bit is architecturally Unpredictable.
For ARM1176JZF-S processors the sticky precise Data Abort bit is
set regardless of DSCR[13]. It is cleared on reads of a DBGTAP
debugger to the DSCR.
The sticky precise data abort bit is only set by precise data aborts
occurring when in Debug state.
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Note
Debug
13-10

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