ARM ARM1176JZF-S Technical Reference Manual page 485

Bits Core view
[5:2] RW
[1] R
[0] R
a. Bits DSCR[11:10] can be controlled by a DBGTAP debugger to execute code in normal state as part of the debugging process.
For example, if the DBGTAP debugger has to execute an OS service to bring a page from disk into memory, and then return
to the application to see the effect this change of state produces, it is undesirable that interrupts are serviced during execution
of this routine.
13.3.4 CP14 c5, Data Transfer Registers (DTR)
ARM DDI 0301H
ID012310
Table 13-4 Debug Status and Control Register bit field definitions (continued)
External Reset
view value
R b0000
R 1
R 0
Bits [5:2] are set to indicate:
• the reason for jumping to the Prefetch or Data Abort vector
• the reason for entering Debug state.
A prefetch abort or data abort handler determines if it must jump to the debug monitor target by
examining the IFSR or DFSR respectively. A DBGTAP debugger or debug monitor target can
determine the specific debug event that caused the Debug state or debug exception entry by
examining DSCR[5:2].
This register consists of two separate physical registers:
• the rDTR, Read Data Transfer Register
• the wDTR, Write Data Transfer Register.
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Description
Method of debug entry bits:
b0000 = a Halt DBGTAP instruction occurred
b0001 = a breakpoint occurred
b0010 = a watchpoint occurred
b0011 = a BKPT instruction occurred
b0100 = an EDBGRQ signal activation occurred
b0101 = a vector catch occurred
b0110 = reserved
b0111 = reserved
b1xxx = reserved.
These bits are set to indicate any of:
• the cause of a Debug Exception
• the cause for entering Debug state
A Prefetch Abort or Data Abort handler must first check the IFSR or
DFSR register to determine a debug exception has occurred before
checking the DSCR to find the cause. These bits are not set on any
events in Debug state.
Core restarted bit:
0 = the processor is exiting Debug state
1 = the processor has exited Debug state.
The DBGTAP debugger can poll this bit to determine when the
processor has exited Debug state. See Debug state on page 13-37 for
a definition of Debug state.
Core halted bit:
0 = the processor is in normal state
1 = the processor is in Debug state.
The DBGTAP debugger can poll this bit to determine when the
processor has entered Debug state. See Debug state on page 13-37 for
a definition of Debug state.
Debug
13-11