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CPSR
Current Program Status Register (CPSR)
Cycles Per instruction (CPI)
CoreSight
Data Abort
Data cache
DBGTAP
Debugger
Debug Test Access Port (DBGTAP)
Default NaN mode
Denormalized value
Direct-mapped cache
Direct Memory Access (DMA)
Dirty
Disabled exception
DMA
DNM
ARM DDI 0301H
ID012310
See Current Program Status Register
The register that holds the current operating processor status.
Cycles per instruction (or clocks per instruction) is a measure of the number of computer
instructions that can be performed in one clock cycle. This figure of merit can be used to
compare the performance of different CPUs that implement the same instruction set against each
other. The lower the value, the better the performance.
The infrastructure for monitoring, tracing, and debugging a complete system on chip.
An indication from a memory system to a core that it must halt execution of an attempted illegal
memory access. A Data Abort is attempting to access invalid data memory.
See also Abort, External Abort, and Prefetch Abort.
A block of on-chip fast access memory locations, situated between the processor and main
memory, used for storing and retrieving copies of often used data. This is done to greatly reduce
the average speed of memory accesses and so to increase processor performance.
See Debug Test Access Port.
A debugging system that includes a program, used to detect, locate, and correct software faults,
together with custom hardware that supports software debugging.
The collection of four mandatory and one optional terminals that form the input/output and
control interface to a JTAG boundary-scan architecture. The mandatory terminals are DBGTDI,
DBGTDO, DBGTMS, and TCK. The optional terminal is TRST. This signal is mandatory in
ARM cores because it is used to reset the debug logic.
A mode in which all operations that result in a NaN return the default NaN, regardless of the
cause of the NaN result. This mode is compliant with the IEEE 754 standard but implies that all
information contained in any input NaNs to an operation is lost.
See Subnormal value.
A one-way set-associative cache. Each cache set consists of a single cache line, so cache look-up
selects and checks a single cache line.
An operation that accesses main memory directly, without the processor performing any
accesses to the data concerned.
A cache line in a write-back cache that has been modified while it is in the cache is said to be
dirty. A cache line is marked as dirty by setting the dirty bit. If a cache line is dirty, it must be
written to memory on a cache miss because the next level of memory contains data that has not
been updated. The process of writing dirty data to main memory is called cache cleaning.
See also Clean.
An exception is disabled when its exception enable bit in the FPCSR is not set. For these
exceptions, the IEEE 754 standard defines the result to be returned. An operation that generates
an exception condition can bounce to the support code to produce the result defined by the
IEEE 754 standard. The exception is not reported to the user trap handler.
See Direct Memory Access.
See Do Not Modify.
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