ARM ARM1176JZF-S Technical Reference Manual page 546

14.6.6 Reset
ARM DDI 0301H
ID012310
Interpreting the PC samples
The PC values read correspond to instructions committed for execution, including those that
failed their condition code. However, these values are offset as Table 13-22 on page 13-33 lists.
These offsets are different for different processor states, so additional information is required:
• If a read request to the PC completes and Data[1:0] equals b00, the read value corresponds
to an ARM state instruction whose 30 most significant bits of the offset address,
instruction address + 8, are given in Data[31:2].
• If a read request to the PC completes and Data[0] equals b1, the read value corresponds
to a Thumb state instruction whose 31 most significant bits of the offset address,
instruction address + 4, are given in Data[31:1].
• If a read request to the PC completes and Data[1:0] equals b10, the read value corresponds
to a Jazelle state instruction whose 30 most significant bits of its address are given in
Data[31:2], the offset is 0. Because of the state encoding, the lower two bits of the Java
address are not sampled. However, the information provided is enough for profiling the
code.
• If the PC is read while the processor is in Debug state, the result is
Scan chains 8-15
These scan chains are reserved.
Scan chains 16-31
These scan chains are unassigned.
The DBGTAP is reset either by asserting DBGnTRST, or by clocking it while DBGTAPSM is
in the Test-Logic-Reset state. The processor, including CP14 debug logic, is not affected by
these events. See Reset modes on page 9-10 and CP14 registers reset on page 13-25 for details.
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Debug Test Access Port
.
0xFFFFFFFF
14-20