ARM ARM966E-S Processor Core Manuals

Manuals and User Guides for ARM ARM966E-S Processor Core. We have 1 ARM ARM966E-S Processor Core manual available for free PDF download: Technical Reference Manual

ARM ARM966E-S Technical Reference Manual

ARM ARM966E-S Technical Reference Manual (190 pages)

Brand: ARM | Category: Computer Hardware | Size: 1 MB

Table of Contents

Table of Contents

3
6.3 Ahb Bus Master Interface

67
Debug Support

93
- Chapter 8 Debug Support
  
  94
- Chapter 9 Embedded Trace Macrocell Interface
  
  119
  - About the ETM Interface
    120
  - Figure 9-1 ARM966E-S ETM Interface
    120
  - Enabling the ETM Interface
    121
  - ARM966E-S Trace Support Features
    122
  - About the ARM966E-S Test Methodology
    124
- Chapter 10 Test Support
  
  124
- Chapter 11 Instruction Cycle Timings
  
  132
- Appendix A Signal Descriptions
  
  144
  - Signal Properties and Requirements
    144
  - Clock Interface Signals
    145
    
    Table A-1 Clock Interface Signals
    145
  - AHB Signals
    146
    
    Table A-2 AHB Signals
    146
    
    A.3 AHB Signals
    146
  - Coprocessor Interface Signals
    148
    
    Table A-3 Coprocessor Interface Signals
    148
  - Debug Signals
    150
    
    Table A-4 Debug Signals
    150
    
    A.5 Debug Signals
    150
  - Miscellaneous Signals
    153
    
    A.6 Miscellaneous Signals
    153
  - ETM Interface Signals
    154
    
    Table A-6 ETM Interface Signals
    154
  - INTEST Wrapper Signals
    156
    
    Table A-7 INTEST Wrapper Signals
    156
  - DMA Signals
    157
    
    Table A-8 DMA Signals
    157
    
    A.9 DMA Signals
    157
- Appendix Bac Parameters
  
  159
  - Timing Diagrams
    159
B.1 Timing Diagrams

160
- AHB Bus Master Timing
  161
- Figure B-2 AHB Bus Request and Grant Related Timing
  161
- Coprocessor Interface Timing
  162
- Figure B-3 AHB Bus Master Timing
  162
- Debug Interface Timing
  163
- Figure B-4 Coprocessor Interface Timing
  163
- Figure B-5 Debug Interface Timing
  164
- JTAG Interface Timing
  164
- Figure B-6 JTAG Interface Timing
  165
- Exception and Configuration Timing
  166
- Figure B-7 DBGSDOUT to DBGTDO Timing
  166
- Figure B-8 Exception and Configuration Timing
  166
- Figure B-9 INTEST Wrapper Timing
  167
- Figure B-10 ETM Interface Timing
  168
- Figure B-11 DMA Interface Timing
  169
- AC Timing Parameter Definitions
  170
  - Table B-1 AC Parameters
    170
- Appendix Csram Stall Cycles
  177
  - About SRAM Stall Cycles
    178
  - Figure
    178
    
    SRAM Write Cycle
    178
    
    Read Follows Write
    178
    
    Simultaneous Instruction Fetch, Data Read
    179
    
    Data Read from I-SRAM
    181
    
    Data Read Followed by Instruction Fetch
    181
    
    Simultaneous Instruction Fetch, Data Write
    182
    
    I-SRAM Data Write Followed by Instruction Fetch
    183
    
    I-SRAM Write Followed by Instruction Fetch, Data Write
    184
    
    I-SRAM Write Followed by Instruction Fetch, Data Read
    185

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