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2.7
Addresses in a processor system
Processor
Virtual Address
ARM DDI 0301H
ID012310
Three distinct types of address exist in the processor system:
•
Virtual Address (VA)
•
Modified Virtual Address (MVA)
•
Physical Address (PA).
When the core is in the Secure world the VA is Secure, and when the core is in the Non-secure
world the VA is Non-secure. To get the VA to PA translation, the core uses Secure pages tables
while it is in Secure world. Otherwise it uses the Non-secure page tables.
Table 2-3 lists the address types in the processor system.
Caches
Virtual index Physical tag
This is an example of the address manipulation that occurs when the processor requests an
instruction, see Figure 1-1 on page 1-8:
1.
The VA of the instruction is issued by the processor, Secure or Non-secure VA according
to the world where the core is.
2.
The Instruction Cache is indexed by the lower bits of the VA. The VA is translated using
the ProcID, Secure or Non-secure one, to the MVA, and then to PA in the Translation
Lookaside Buffer (TLB). The TLB performs the translation in parallel with the Cache
lookup. The translation uses Secure descriptors if the core is in Secure world. Otherwise
it uses the Non-secure ones.
3.
If the protection check carried out by the TLB on the MVA does not abort and the PA tag
is in the Instruction Cache, the instruction data is returned to the processor.
4.
The PA is passed to the AXI bus interface to perform an external access, in the event of a
cache miss. The external access is always Non-secure when the core is in Non-secure
world. In Secure world, the external access is Secure or Non-secure according to the NS
attribute value in the selected descriptor.
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Table 2-3 Address types in the processor system
TLBs
Translates Virtual Address to Physical Address
Programmer's Model
AXI bus
Physical Address
2-16
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