Timing Of The Vic Port; Figure 12-2 Vic Port Timing Example - ARM ARM1176JZF-S Technical Reference Manual

12.3

Timing of the VIC port

Processor
clock
Peripheral port
HCLK
IRQADDR[31:2]
nIRQ
IRQACK
IRQADDRV
ARM DDI 0301H
ID012310
Figure 12-2 shows a timing example of VIC port operation. In this example IRQC is received
followed by IRQB having a higher priority. The waveforms in Figure 12-2 show an
asynchronous relationship between CLKIN and HCLK, and the delays marked Sync cater for
the delay of the synchronizers. When this interface is used synchronously, these delays are
reduced to being a single cycle of the receiving clock.
B1 B2 B3 B4
IRQC vector address
Figure 12-2 illustrates the basic handshake mechanism that operates between the processor and
a PL192 VIC:
An IRQC interrupt request occurs causing the PL192 VIC to set the processor nIRQ
1.
input.
The processor samples the nIRQ input LOW and initiates an interrupt entry sequence.
2.
3. Another IRQB interrupt request of higher priority than IRQC occurs.
4. Between B3 and B4, the processor decides that the pending interrupt is an IRQ rather than
a FIQ and asserts the IRQACK signal.
At B4 the VIC samples IRQACK HIGH and starts generating IRQADDRV. The VIC
5.
can still change IRQADDR to the IRQB vector address while IRQADDRV is LOW.
At B6 the VIC asserts IRQADDRV while IRQADDR is set to the IRQB vector address.
6.
IRQADDR is held until the processor acknowledges it has sampled it, even if a higher
priority interrupt is received while the VIC is waiting.
Around B8 the processor samples the value of the IRQADDR input bus and deasserts
7.
IRQACK.
When the VIC samples IRQACK LOW, it stacks the priority of the IRQB interrupt and
8.
deasserts IRQADDRV. It also deasserts nIRQ if there are no higher priority interrupts
pending.
When the processor samples IRQADDRV LOW, it knows it can sample the nIRQ input
9.
again. Therefore, if the VIC requires some time for deasserting nIRQ, it must ensure that
IRQADDRV stays HIGH until nIRQ has been deasserted.
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B5 B6 B7 B8
IRQB vector address
Address sampled
Sync

Figure 12-2 VIC port timing example

Vectored Interrupt Controller Port
B9 B10 B11 B12
12-5