Table 13-13 Processor Watchpoint Value Registers - ARM ARM1176JZF-S Technical Reference Manual

13.3.9 CP14 c96-c97, Watchpoint Value Registers (WVR)
Binary address
Opcode_2
b110
ARM DDI 0301H
ID012310
• The BCR[8:5] field is treated as part of the compared address, For an IMVA mismatch the
bits must be set to 1 for the corresponding byte lanes that are excluded from the
breakpoint.
The following rules apply to the processor for breakpoint debug event generation:
• The update of a BVR or a BCR can take effect several instructions after the corresponding
MCR. It takes effect by the next IMB.
• Updates of the CP15 Context ID Register c13, can take effect several instructions after the
corresponding MCR. However, the write takes place by the end of the exception return.
This is to ensure that a User mode process, switched in by a processor scheduler, can break
at its first instruction.
• Any BRP, holding an IMVA, can be linked with any other one with context ID capability.
Several BRPs, holding IMVAs, can be linked with the same context ID capable one.
• If a BRP, holding an IMVA, is linked with one that is not configured for context ID
comparison and linking, it is architecturally Unpredictable whether a breakpoint debug
event is generated or not. For ARM1176JZF-S processors the breakpoint debug event is
not generated. BCR[22:20] fields of the second BRP must be set to b011.
• If a BRP, holding an IMVA, is linked with one that is not implemented, it is architecturally
Unpredictable if a breakpoint debug event is generated or not. For ARM1176JZF-S
processors the breakpoint debug event is not generated.
• If a BRP is linked with itself, it is architecturally Unpredictable if a breakpoint debug
event is generated or not. For ARM1176JZF-S processors the breakpoint debug event is
not generated.
• If a BRP, holding an IMVA, is linked with another BRP, holding a context ID value, and
they are not both enabled, both BCR[0] bits set, the first one does not generate any
breakpoint debug event.
Each WVR is associated with a WCR register. WCRy is the corresponding register for WVRy.
A pair of watchpoint registers, WVRy and WCRy, is called a Watchpoint Register Pair (WRP).
WVR0-1 are paired with WCR0-1 to make WRP0-1.
Table 13-13 lists the Watchpoint Value Registers that the processor implements.
Register
number
CRm
b0000-b0001 c96-c97
The watchpoint value contained in the WVR always corresponds to a DMVA. Watchpoints can
be set on:
• a DMVA
• a DMVA/context ID pair.
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Table 13-13 Processor Watchpoint Value Registers

CP14 debug register name
Watchpoint Value Registers 0-1
Debug
Context ID
Abbreviation
capable?
WVR0-1 -
13-20