Figure - ARM ARM1176JZF-S Technical Reference Manual

B.2.2 ARMv6k extensions support
B.2.3 Power management
ARM DDI 0301H
ID012310
— Opcode_2=0.
The ARM1176JZF-S processor adds extra support for the ARMv6k extensions that are not
present in the ARM1136JF-S r0p2 processor.
Note
These extensions are present in the ARM1136JF-S r1p0 processor though.
This includes:
• New Store and Load Exclusive instructions for bytes, halfwords and doublewords and a
new Clear Exclusive instruction.
• A new true no-operation instruction and yield instruction.
• Architectural remap registers. The memory remap registers in the ARM1136JF-S
processor are replaced by registers in CP15 c10 in the ARM1176JZF-S processor.
• Cache size restriction through CP15 c1. Cache size can be restricted to 16KB for OSs that
do not support page coloring.
• Revised use of TEX bits.
• Revised use of AP bits.
Behavior of TEX bits
The ARMv6 MMU page table descriptors use a large number of bits to describe all of the
options for inner and outer cachability. In reality, it is believed that no application requires all of
these options simultaneously. Therefore, it is possible to configure the ARM1176JZF-S
processor to support only a small number of options by means of the TEX remap mechanism.
This implies a level of indirection in the page table mappings.
Recent cores, that include ARM1136JF-S processors support this mapping with the MMU
remap capability, that was originally designed for debug of the hardware, in CP15 register 15.
By moving one entry in the ARM1176JZF-S processor TEX CB encoding table, with an alias
for compatibility, TEX[2:1] is freed for use as two OS managed page table bits. Because binary
compatibility is important with existing ARMv6 ports of OSs, this change consists of a separate
mode of operation of the MMU. This is called the TEX remap configuration and is controlled
by bit [28] TR in CP15 Register 1. The MMU remap registers, other than the Peripheral Remap
Register, become architectural and move from CP15 register 15 to CP15 register 10.
Access permissions
In the ARM1176JZF-S processor the APX and AP[1:0] encoding b111 becomes Privileged or
User mode read only access. This releases AP[0] to indicate a new abort type, Access Bit fault,
when CP15 c1[29] is 1. In theARM1136JF-S the encoding b111 was reserved.
The differences in power management between the ARM1136JF-S and ARM1176JZF-S
processors are in two areas:
• Intelligent Energy Management on page B-5
• VFP on page B-5.
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Summary of ARM1136JF-S and ARM1176JZF-S Processor Differences
B-4