ARM ARM1176JZF-S Technical Reference Manual page 72

Operation
Store
Push/Pop
Change state
Byte-reverse
Supervisor call
Software breakpoint
Sign or zero extend
ARM DDI 0301H
ID012310
Signed halfword
Byte
Signed byte
PC-relative
SP-relative
Multiple
With immediate offset
Word
Halfword
Byte
With register offset
Word
Halfword
Byte
SP-relative
Multiple
Push registers onto stack
Push LR and registers onto stack
Pop registers from stack
Pop registers and PC from stack
Change processor state
Change endianness
Byte-reverse word
Byte-reverse halfword
Byte-reverse signed halfword
Sign extend 16 to 32
Sign extend 8 to 32
Zero extend 16 to 32
Zero extend 8 to 32
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Table 1-16 Thumb instruction set summary (continued)
Introduction
Assembler
LDRSH <Rd>, [<Rn>, <Rm>]
LDRB <Rd>, [<Rn>, <Rm>]
LDRSB <Rd>, [<Rn>, <Rm>]
LDR <Rd>, [PC, #<immed_8*4>]
LDR <Rd>, [SP, #<immed_8*4>]
LDMIA <Rn>!, <reglist>
-
STR <Rd>, [<Rn>, #<immed_5*4>]
STRH <Rd>, [<Rn>, #<immed_5*2>]
STRB <Rd>, [<Rn>, #<immed_5>]
-
STR <Rd>, [<Rn>, <Rm>]
STRH <Rd>, [<Rn>, <Rm>]
STRB <Rd>, [<Rn>, <Rm>]
STR <Rd>, [SP, #<immed_8*4>]
STMIA <Rn>!, <reglist>
PUSH <reglist>
PUSH <reglist, LR>
POP <reglist>
POP <reglist, PC>
CPS <effect> <iflags>
SETEND <endian_specifier>
REV <Rd>, <Rm>
REV16 <Rd>, <Rm>
REVSH <Rd>, <Rm>
SVC <immed_8>
BKPT <immed_8>
SXTH<Rd>, <Rm>
SXTB<Rd>, <Rm>
UXTH<Rd>, <Rm>
UXTB<Rd>, <Rm>
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