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Byte-invariant
Byte lane strobe
Byte swizzling
Cache
Cache contention
Cache hit
Cache line
Cache line index
Cache lockdown
Cache miss
Cache set
Cache way
Cast out
ARM DDI 0301H
ID012310
In a byte-invariant system, the address of each byte of memory remains unchanged when
switching between little-endian and big-endian operation. When a data item larger than a byte
is loaded from or stored to memory, the bytes making up that data item are arranged into the
correct order depending on the endianness of the memory access.
The ARM architecture supports byte-invariant systems in ARMv6 and later versions. When
byte-invariant support is selected, unaligned halfword and word memory accesses are also
supported. Multi-word accesses are expected to be word-aligned.
See also Word-invariant.
An AXI signal, WSTRB, that is used for unaligned or mixed-endian data accesses to determine
which byte lanes are active in a transfer. One bit of WSTRB corresponds to eight bits of the data
bus.
The reverse ordering of bytes in a word.
A block of on-chip or off-chip fast access memory locations, situated between the processor and
main memory, used for storing and retrieving copies of often used instructions and/or data. This
is done to greatly reduce the average speed of memory accesses and so to increase processor
performance.
See also Cache terminology diagram on the last page of this glossary.
When the number of frequently-used memory cache lines that use a particular cache set exceeds
the set-associativity of the cache. In this case, main memory activity increases and performance
decreases.
A memory access that can be processed at high speed because the instruction or data that it
addresses is already held in the cache.
The basic unit of storage in a cache. It is always a power of two words in size (usually four or
eight words), and is required to be aligned to a suitable memory boundary.
See also Cache terminology diagram on the last page of this glossary.
The number associated with each cache line in a cache way. Within each cache way, the cache
lines are numbered from 0 to (set associativity) -1.
See also Cache terminology diagram on the last page of this glossary.
To fix a line in cache memory so that it cannot be overwritten. Cache lockdown enables critical
instructions and/or data to be loaded into the cache so that the cache lines containing them are
not subsequently reallocated. This ensures that all subsequent accesses to the instructions/data
concerned are cache hits, and therefore complete as quickly as possible.
A memory access that cannot be processed at high speed because the instruction/data it
addresses is not in the cache and a main memory access is required.
A cache set is a group of cache lines (or blocks). A set contains all the ways that can be
addressed with the same index. The number of cache sets is always a power of two.
See also Cache terminology diagram on the last page of this glossary.
A group of cache lines (or blocks). It is 2 to the power of the number of index bits in size.
See also Cache terminology diagram on the last page of this glossary.
See Victim.
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