Mmu Descriptors; Table 6-13 Translation Table Size - ARM ARM1176JZF-S Technical Reference Manual

6.12

MMU descriptors

6.12.1 First-level descriptor address
ARM DDI 0301H
ID012310
To support sections and pages, the processor MMU uses a two-level descriptor definition. The
first-level descriptor indicates whether the access is to a section or to a page table. If the access
is to a page table, the processor MMU determines the page table type and fetches a second-level
descriptor.
The ARM1176 contains:
• two Translation Table Base Registers, TTBR0 and TTBR1
• one Translation Table Base Control Register (TTBCR).
On a TLB miss, the top bits of the modified virtual address determine whether the first or second
Translation Table Base is used. Figure 6-10 on page 6-44 shows the creation of a first-level
descriptor address.
The expected use of two translation tables is to reduce the cost of OS context switches by
enabling the OS, and each individual task or process, to have its own pagetable without
consuming much memory.
In this model, the virtual address space is divided into two regions:
• 0x0 -> 1<<(32-N) that TTBR0 controls
• 1<<(32-N) -> 4GB that TTBR1 controls.
The value of N is set in the TTBCR. If N is zero, then TTBR0 is used for all addresses, and that
gives legacy v5 behavior. If N is not zero, the OS and memory mapped IO are located in the
upper part of the memory map, TTBR1, and the tasks or processes all occupy the same virtual
address space in the lower part of the memory, TTBR0.
The TTBCR, TTBR0, and TTBR1 registers used for this process are banked. Depending on the
state of the MMU requests that cause a page table walk, either Secure or Non-secure registers
are used.
The translation table that TTBR0 points to can be truncated because it must only cover the first
1<<(32-N) bytes of memory. The first entry always corresponds to address
mechanism is more efficient if processes start at a low virtual address such as
Table 6-13 lists the translation table size.
N
0
1
2
3
4
5
6
7
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Upper boundary Translation table 0 size
4GB 16KB, 4096 entries, v5 behavior, TTBR1 not used.
2GB 8KB, 2048 entries
1GB 4KB, 1024 entries
512MB 2KB, 512 entries
256MB 1KB, 256 entries
128MB 512B, 128 entries
64MB 256B, 64 entries
32MB 128B, 32 entries
Memory Management Unit
0x0 , so this
or
0x0 0x8000

Table 6-13 Translation table size

.
6-43